module tizedikhazi(
input bemenet,
input clk,
output reg kimenet
);

reg [3:0]tarolo;
reg [3:0]counter;

always @(posedge clk)begin
        if(counter == 4'b0011)      counter <= 0;
        else                        counter <= counter+1;

        tarolo <= {tarolo[2:0],bemenet};

        if(tarolo == 4'b1001 && counter == 4'b0011)
            kimenet <= 1;
        else
            kimenet <= 0;
end

endmodule