9x11

module LCD_CTRL(clk, reset, datain, cmd, cmd_valid, dataout, output_valid, busy);

input clk;
input reset;
input [7:0] datain;
input [2:0] cmd;
input cmd_valid;

output reg [7:0] dataout;
output reg output_valid;
output reg busy;

reg [7:0]in[107:0]; //8 bits reg and there are total 108
reg [2:0]state;
reg [7:0]out[15:0];

reg [3:0]x,y;
reg [7:0]origin;

integer i;
parameter [2:0]S0=3'b0,[2:0]S0=3'b001,[2:0]S0=3'b010,[2:0]S0=3'b011
            ,[2:0]S0=3'b100,[2:0]S0=3'b101,[2:0]S0=3'b110,[2:0]S0=3'b111;
//assign dataout = out;

always@(*)
begin
    origin[7:4] <= x[3:0] ;
    origin[3:0] <= y[3:0] ;
end

always@(posedge clk)
begin
if(reset)
    i <= 0;
else if( i == 107)
    i <= 0;
else


end


always@(posedge clk or posedge reset)
begin
if(reset)
begin
    x <= 1'h0;
    y <= 1'h0;
    origin <= 2'h00;
    in <= 0;
end

else if( x == 4'b1011 )
begin
    if( y == 4'b1000)
    begin
        x <= 1'h0;
        y <= 1'h0;
    end
    y <= y + 4'b0001 ;
end

else
begin
    x <= x + 4'b0001 ;
end
end


always@(posedge clk)
begin
if(reset)
begin
    dataout <= 2'h00;
    output_valid <= 1'b0;
    busy <= 1'b0;
end

else
begin
    if(cmd_valid)
    begin
        case(cmd)
        S0:begin

        end

        S1:begin

        end

        S2:begin

        end

        S3:begin

        end

        S4:begin

        end

        S5:begin

        end

        S6:begin

        end

        S7:begin

        end

    end



end

end

endmodule