vim3 uboot log

G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;0.
bl2_stage_init 0x01
bl2_stage_init 0x81
hw id: 0x0000 - pwm id 0x01
bl2_stage_init 0xc1
bl2_stage_init 0x02

L0:00000000
L1:20000703
L2:00008067
L3:14000000
B2:00402000
B1:e0f83180

TE: 172072

BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz

Board ID = 8
Set A53 clk to 24M
Set A73 clk to 24M
Set clk81 to 24M
A53 clk: 1200 MHz
A73 clk: 1200 MHz
CLK81: 166.6M
smccc: 0002e806
eMMC boot @ 0
sw8 s
DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
board id: 8
Load FIP HDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
fw parse done
Load ddrfw from eMMC, src: 0x00060200, des: 0xfffd0000, size: 0x0000c000, part: 0
Load ddrfw from eMMC, src: 0x00038200, des: 0xfffd0000, size: 0x00004000, part: 0
PIEI prepare done
fastboot data load
00000000
emmc switch 1 ok
ddr saved addr:00016000
Load ddr parameter from eMMC, src: 0x02c00000, des: 0xfffd0000, size: 0x00001000, part: 0
00000000
emmc switch 0 ok
fastboot data verify
verify result: 265
Cfg max: 4, cur: 1. Board id: 255. Force loop cfg
LPDDR4 probe
ddr clk to 1608MHz
Load ddrfw from eMMC, src: 0x0003c200, des: 0xfffd0000, size: 0x0000c000, part: 0

dmc_version 0001
Check phy result
INFO : End of CA training
INFO : End of initialization
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of Write leveling coarse delay
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : End of write delay center optimization
INFO : End of read delay center optimization
INFO : End of max read latency training
INFO : Training has run successfully!
1D training succeed
Load ddrfw from eMMC, src: 0x00048200, des: 0xfffd0000, size: 0x0000c000, part: 0
Check phy result
INFO : End of initialization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : Training has run successfully!

channel==0
RxClkDly_Margin_A0==77 ps 8
TxDqDly_Margin_A0==106 ps 11
RxClkDly_Margin_A1==87 ps 9
TxDqDly_Margin_A1==106 ps 11
TrainedVREFDQ_A0==26
TrainedVREFDQ_A1==26
VrefDac_Margin_A0==28
DeviceVref_Margin_A0==26
VrefDac_Margin_A1==28
DeviceVref_Margin_A1==26


channel==1
RxClkDly_Margin_A0==87 ps 9
TxDqDly_Margin_A0==106 ps 11
RxClkDly_Margin_A1==97 ps 10
TxDqDly_Margin_A1==106 ps 11
TrainedVREFDQ_A0==26
TrainedVREFDQ_A1==25
VrefDac_Margin_A0==27
DeviceVref_Margin_A0==25
VrefDac_Margin_A1==26
DeviceVref_Margin_A1==25

 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004

soc_vref_reg_value 0x 00000024 00000025 00000026 00000024 00000024 00000025 00000024 00000025 00000025 00000026 00000024 00000025 00000025 00000024 00000027 00000026 00000025 00000026 00000026 4
2D training succeed
aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
auto size-- 65535DDR cs0 size: 2048MB
DDR cs1 size: 2048MB
DMC_DDR_CTRL: 00e00024DDR size: 3928MB
cs0 DataBus test pass
cs1 DataBus test pass
cs0 AddrBus test pass
cs1 AddrBus test pass

non-sec scramble use zero key
ddr scramble enabled

100bdlr_step_size ps== 444
result report
boot times 2Enable ddr reg access
00000000
emmc switch 3 ok
Authentication key not yet programmed
get rpmb counter error 0x00000007
00000000
emmc switch 0 ok
Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x000d0000, part: 0
0.0;M3 CHK:0;cm4_sp_mode 0
MVN_1=0x00000000
MVN_2=0x00000000
[Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
OPS=0x10
ring efuse init
chipver efuse init
29 0b 10 00 01 25 0a 00 00 0d 35 37 4d 4d 4e 50
[0.972794 Inits done]
secure task start!
high task start!
low task start!
run into bl31
NOTICE:  BL31: v1.3(release):4fc40b1
NOTICE:  BL31: Built : 15:58:17, May 22 2019
NOTICE:  BL31: G12A normal boot!
NOTICE:  BL31: BL33 decompress pass
ERROR:   Error initializing runtime service opteed_fast


U-Boot 2015.01 (Dec 31 2019 - 00:36:50)

DRAM:  3.8 GiB
Relocation Offset is: d6e46000
spi_post_bind(spifc): req_seq = 0
register usb cfg[0][1] = 00000000d7f39548
aml_i2c_init_port init regs for 0
MMC:   aml_priv->desc_buf = 0x00000000d3e36a70
aml_priv->desc_buf = 0x00000000d3e38db0
SDIO Port B: 0, SDIO Port C: 1
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x3, tx-dly 0, clock 400000
emmc/sd response timeout, cmd8, status=0x3ff2800
emmc/sd response timeout, cmd55, status=0x3ff2800
co-phase 0x3, tx-dly 0, clock 400000
co-phase 0x1, tx-dly 0, clock 40000000
aml_sd_retry_refix[983]:delay = 0x0,gadjust =0x22000
[mmc_startup] mmc refix success
init_part() 297: PART_TYPE_AML
[mmc_init] mmc init success
start dts,buffer=00000000d3e3b620,dt_addr=00000000d3e3b620
get_partition_from_dts() 91: ret 0
parts: 3
00:      logo   0000000000800000 1
01:   ramdisk   0000000002000000 1
02:    rootfs   ffffffffffffffff 4
init_part() 297: PART_TYPE_AML
eMMC/TSD partition table have been checked OK!
crc32_s:0x1577dad == storage crc_pattern:0x1577dad!!!
crc32_s:0xee152b83 == storage crc_pattern:0xee152b83!!!
crc32_s:0x79f50f07 == storage crc_pattern:0x79f50f07!!!
mmc env offset: 0x6c00000
In:    serial
Out:   serial
Err:   serial
reboot_mode=watchdog_reboot
[store]To run cmd[emmc dtb_read 0x1000000 0x40000]
_verify_dtb_checksum()-3477: calc 8caae72a, store 8caae72a
_verify_dtb_checksum()-3477: calc 8caae72a, store 8caae72a
dtb_read()-3694: total valid 2
update_old_dtb()-3675: do nothing
aml_i2c_init_port init regs for 0
fusb302_init: Device ID: 0x91
CC connected in 1 as UFP
fusb302 detect chip.port_num = 0

amlkey_init() enter!
[EFUSE_MSG]keynum is 1
vpu: clk_level in dts: 7
vpu: vpu_power_on
vpu: set clk: 666667000Hz, readback: 666666667Hz(0x100)
vpu: vpu_module_init_config
vpp: vpp_init
vpp: vpp osd2 matrix rgb2yuv..............
cvbs: cpuid:0x29
LCD_RESET PIN: 0
lcd: detect mode: tablet, key_valid: 0
lcd: detect lcd_clk_path: 1
lcd: failed to get lcd_cpu_gpio_names
lcd: load config from dts
lcd: pinctrl_version: 2
lcd: use panel_type=lcd_0
lcd: bl: pinctrl_version: 2
lcd: bl: name: backlight_pwm, method: 1
lcd: bl: aml_bl_power_ctrl: 0
Net:   __phy_realtek_initdwmac.ff3f0000
amlkey_init() enter!
amlkey_init() 71: already init!
[EFUSE_MSG]keynum is 1
MACADDR:02:00:00:0a:25:01(from chipid)

upgrade_step=0
reboot_mode:::: watchdog_reboot

amlkey_init() enter!
amlkey_init() 71: already init!
[EFUSE_MSG]keynum is 1
[KM]Error:f[key_manage_query_size]L515:key[usid] not programed yet

mac address: c8:63:14:70:62:b9
[KM]Error:f[key_manage_query_size]L515:key[deviceid] not programed yet
edid preferred_mode is <NULL>[0]
hdr mode is 0
dv  mode is ver:0  len: 0
hdr10+ mode is 0
HDMI cable is NOT connected
hpd_state=0
[OSD]load fb addr from dts:/meson-fb
[OSD]set initrd_high: 0x7f800000
[OSD]fb_addr for logo: 0x7f800000
[OSD]load fb addr from dts:/meson-fb
[OSD]fb_addr for logo: 0x7f800000
[OSD]VPP_OFIFO_SIZE:0xfff01fff
[CANVAS]canvas init
[CANVAS]addr=0x7f800000 width=5760, height=2160
card in
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 40000000
aml_sd_retry_refix[983]:delay = 0x0,gadjust =0x22000
[mmc_startup] mmc refix success
init_part() 282: PART_TYPE_DOS
[mmc_init] mmc init success
750054 bytes read in 81 ms (8.8 MiB/s)
[OSD]osd_hw.free_dst_data: 0,1079,0,1919
[OSD]osd1_update_disp_freescale_enable
cvbs: outputmode[panel] is invalid
hdmitx: outputmode[panel] is invalid
vpp: vpp_matrix_update: 0
vpp: g12a/b post2(bit12) matrix: YUV limit -> RGB ..............
lcd: enable: TS050, mipi, [email protected]
lcd: tablet driver init(ver 20180718): mipi
lcd: lcd_pll_wait_lock: pll_lock=1, wait_loop=1
vpp: vpp_init_lcd_gamma_table
lcd: pixel_clk = 120.000MHz, bit_rate = 960.000MHz, lanebyteclk = 120.000MHz
lcd:  Waiting STOP STATE LANE
lcd: dsi init on
lcd: bl: set level: 100, last level: 0
lcd: bl: aml_bl_power_ctrl: 1
lcd: clear mute
vpp: Rx hdr_info.hdr_sup_eotf_smpte_st_2084 = 0

amlkey_init() enter!
amlkey_init() 71: already init!
[EFUSE_MSG]keynum is 1
[KM]Error:f[key_manage_query_size]L515:key[usid] not programed yet

mac address: c8:63:14:70:62:b9
[KM]Error:f[key_manage_query_size]L515:key[deviceid] not programed yet
gpio: pin GPIOAO_7 (gpio 7) value is 1
saradc: 0x286, hw_ver: 0x32 (VIM3.V12)
Product checking: pass! Hardware version: VIM3.V12
reboot_mode=watchdog_reboot
normal power on
boot wol: disable
port mode is usb3.0
Hit Enter or space or Ctrl+C key to stop autoboot -- :  0
Device: SDIO Port B
Manufacturer ID: 1b
OEM: 534d
Name: FB4HT
Tran Speed: 50000000
Rd Block Len: 512
SD version 3.0
High Capacity: Yes
Capacity: 29.8 GiB
mmc clock: 40000000
Bus Width: 4-bit
reading s905_autoscript
8600 bytes read in 6 ms (1.4 MiB/s)
## Executing script at 01020000
Starting S905 autoscript...
saradc: 0x286, hw_ver: 0x32 (VIM3.V12)
uboot type: vendor
autoscript loaded from: mmc
Scanning mmc 0:1...
reading uInitrd
11971430 bytes read in 657 ms (17.4 MiB/s)
reading zImage
21331976 bytes read in 1170 ms (17.4 MiB/s)
reading dtb.img
51400 bytes read in 6 ms (8.2 MiB/s)
reading /boot/env.txt
** Unable to read file /boot/env.txt **
reading env.txt
2760 bytes read in 3 ms (898.4 KiB/s)
Import env.txt
Booting mainline kernel...
libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND
port mode is usb3.0
HDMI: Autodetect: 1080p60hz
libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND
[rsvmem] fdt get prop fail.
## Loading init Ramdisk from Legacy Image at 13000000 ...
   Image Name:   uInitrd
   Image Type:   AArch64 Linux RAMDisk Image (gzip compressed)
   Data Size:    11971366 Bytes = 11.4 MiB
   Load Address: 00000000
   Entry Point:  00000000
   Verifying Checksum ... OK
load dtb from 0x1000000 ......
ERROR: Did not find a cmdline Flattened Device Tree
load dtb from 0x0 ......
ERROR: Did not find a cmdline Flattened Device Tree
Could not find a valid device tree
Scanning mmc 0:5...
** Invalid partition 5 **
Scanning mmc 1:1...
** Unrecognized filesystem type **
Scanning mmc 1:5...
8469162 bytes read in 243 ms (33.2 MiB/s)
28979712 bytes read in 816 ms (33.9 MiB/s)
87858 bytes read in 8 ms (10.5 MiB/s)
2701 bytes read in 4 ms (659.2 KiB/s)
Import env.txt
Can not get u-boot part UUID, set to NULL
Booting legacy kernel...
port mode is usb3.0
HDMI: Autodetect: 1080p60hz
## Loading init Ramdisk from Legacy Image at 13000000 ...
   Image Name:   uInitrd
   Image Type:   AArch64 Linux RAMDisk Image (gzip compressed)
   Data Size:    8469098 Bytes = 8.1 MiB
   Load Address: 00000000
   Entry Point:  00000000
   Verifying Checksum ... OK
load dtb from 0x1000000 ......
## Flattened Device Tree blob at 01000000
   Booting using the fdt blob at 0x1000000
   reserving fdt memory region: addr=1000000 size=16000
   Loading Ramdisk to 7efec000, end 7f7ffa6a ... OK
   Loading Device Tree to 000000001ffe7000, end 000000001fffffff ... OK

Starting kernel ...

uboot time: 7694867 us
[    0.000000@0] Booting Linux on physical CPU 0x0
[    0.000000@0] Linux version 4.9.206 (khadas@3a97a4844f91) (gcc version 7.3.1 20180425 [linaro-7.3-2018.05 revision d29120a424ecfbc167ef90065c0eeb7f91977701] (Linaro GCC 7.3-2018.05) ) #13 SM9
[    0.000000@0] Boot CPU: AArch64 Processor [410fd034]