module SimpleUART(CLOCK_50,KEY,KEY1,TXPIN);

input CLOCK_50;
input KEY;
input KEY1;
output TXPIN;

reg [15:0]  count;
reg [15:0]  cSpeed = 16'b101000101100;
reg ClkOut = 1'b0;

always@(posedge CLOCK_50)

begin
    if(count == cSpeed)
        begin
            count = 0;
            ClkOut = ~ClkOut;
        end
    else
        count = count + 1;
end

assign KEYA = KEY;
assign KEYB = KEY1;

always@(posedge ClkOut)
begin
    if(!KEYA)
    begin
        tx_enable = 1'b1;
        tx_reg = 8'b01001010;
    end

    if(!KEYB)
    begin
        tx_enable = 1'b1;
        tx_reg = 8'b01000001;
    end

    if(KEYB && KEYA)
        tx_enable <= 0;

end


reg [7:0]    tx_reg         ;
reg [3:0]    tx_cnt         ;
reg          tx_out         ;
reg              tx_enable;

// UART TX Logic
always @ (posedge ClkOut)
begin
   if (tx_enable) begin
     if (tx_cnt == 0) begin
       tx_out <= 0;
     end
     if (tx_cnt > 0 && tx_cnt < 9) begin
        tx_out <= tx_reg[tx_cnt -1];
     end
     if (tx_cnt == 9) begin
       tx_out <= 1;
       tx_cnt <= 0;
         tx_cnt <= 0;
     end
      tx_cnt <= tx_cnt + 1;
   end

end

assign TXPIN = tx_out;
endmodule