View difference between Paste ID: vf5VPyvd and DFfKasDc

 `timescale 1ns / 1ps
 
 module clock_out(
 						input clk,
 						input rest,
 						output out_clk
 
     );
 
 reg  [18:0] ctr;
 assign out_clk = ctr[17];
 always@ (posedge clk) begin
 if (rest==1'b1) ctr=0;
 else ctr=ctr+1;
 
 
 end
 
 endmodule
 
 module vm(		input clk,
 					input rest,
 					input reset,
 					output reg [3:0] EN,
 					output reg [7:0] y,
 					output [18:0] ctr,
 					output out_clk
 		 			);
 clock_out co (.clk(clk), .rest(rest), .out_clk(out_clk));
 
 always@(posedge out_clk) begin
 
 			if (reset==1) begin
 			EN=4'b1110;
 			y=8'b11111110;
 			end
 
 			else begin
 			if (y[7]==0) EN=(EN<<1|EN>>3);
 			y =(y<<1)|(y>>7);
 
 			end
 end
 
 endmodule