View difference between Paste ID: hGrc9Jtt and Lm1KnHXr

-Summary of video interfaces/formats supported:
+                    ioset 1             ioset 2             ioset 3
 vin 1.1a clk         28    -            116 -               167 P9.22a
-8-bit interface:
+vin 1.1a de          48/44 -            115 P8.30a          168 P9.41a
-- YUV422 (interleaved) with discrete sync or embedded sync (BT.656).
+vin 1.1a fld         27/39 -            114 P8.28a          164 -
-- pixel- or line-multiplexed multi-video stream with embedded sync.
+vin 1.1a hsync       29/48 -            117 P8.29a          162 P9.26a
 vin 1.1a vsync       30/49 -            118 P8.27a          163 P9.24
-16-bit interface:
+vin 1.1a d0          16    P9.19a       135 P8.45b          171 P9.12
-- RGB565 with discrete sync.  Can alternatively use d3-d7 + d10-d15 + d19-d23.
+vin 1.1a d1          17    P9.20a       136 P9.11b          172 P9.27b
-- YUV422 (separate luma/chroma) with discrete sync or embedded sync (BT.1120).
+vin 1.1a d2          18    -            137 P8.17           175 -
 vin 1.1a d3          19    -            138 P8.27b          176 -
-24-bit interface:
+vin 1.1a d4          20    -            139 P8.28b          177 -
-- RGB888 or YUV444 with discrete sync or embedded sync (BT.1120).
+vin 1.1a d5          21    -            140 P8.29b          178 -
 vin 1.1a d6          22    -            141 P8.30b          179 -
-"Embedded sync" means synchronization markers are embedded in the video data stream,
+vin 1.1a d7          23    -            142 P8.46b          180 -
-similar to the sync pulses embedded in analog composite video signals, and therefore the
+vin 1.1a d8          31    -            127 P8.37a          191 -
-interface only uses clk + data lines, no separate synchronization signals.
+vin 1.1a d9          32    -            128 P8.38a          192 -
 vin 1.1a d10         33    -            129 P8.36a          193 -
-"Discrete sync" means separate vsync/hsync/de/fld signals (or some subset thereof) are
+vin 1.1a d11         34    -            130 P8.34a          194 -
-used to synchronize to the video timing.  To use discrete sync, the video input port
+vin 1.1a d12         35    -            131 P8.35a          197 -
-requires at least vsync+hsync or vsync+de.  Interleaved video additionally needs either
+vin 1.1a d13         36    -            132 P8.33a          198 -
-fld or vsync+hsync (in the latter case the field identification is determined by timing
+vin 1.1a d14         37    -            133 P8.31a          199 -
-of vsync relative to hsync, same as in analog video).
+vin 1.1a d15         38    -            134 P8.32a          200 -
 vin 1.1a d16          -    -            119 P8.45a          205 P8.38b
 vin 1.1a d17          -    -            120 P8.46a          206 P8.37b
-======== vin4a (VIP2 slice 1 input A) ========
+vin 1.1a d18          -    -            121 P8.43           207 P8.31b
 vin 1.1a d19          -    -            122 P8.44           208 P8.32b
-It's a mix of different iosets so timing is probably degraded (unless you manage
+vin 1.1a d20          -    -            123 P8.41           209 -
-to tune the iodelay manually), which will limit the max pixel clock supported.
+vin 1.1a d21          -    -            124 P8.42           210 -
 vin 1.1a d22          -    -            125 P8.39           211 -
-Nearly a full-featured input, except only 23 of the 24 data signals are available;
+vin 1.1a d23          -    -            126 P8.40           212 -
-you can pick any two of { d7, d8, d17 } but not all three.
+
 
-For 24-bit RGB or YUV444, sacrificing d8 is probably the best option, since it is the
+                    ioset 2             ioset 3
-least significant bit of one channel.  By default it will be green (for RGB) or Cb
+vin 0.1b clk         87 -               232 P8.04
-(for YUV), but you can use the "repacker" to swap channels and e.g. make d8 the least
+vin 0.1b de          86 -               231 P8.03
-significant bit of the _blue_ channel instead to minimize the visual impact of its loss.
+vin 0.1b hsync       88 -               221 -
 vin 0.1b vsync       89 P8.34b          222 -
-For 16-bit RGB or YUV422 input on d0-d15, you don't need d17 so there's no problem.
+vin 0.1b d0         113 -               230 P8.22
-RGB565 can also be provided on d3-d7 (blue) + d10-d15 (green) + d19-d23 (red), i.e. the
+vin 0.1b d1         112 -               229 P8.23
-most significant bits of RGB888.  In this case neither d8 nor d17 is used.
+vin 0.1b d2         111 P8.16           228 P8.06
 vin 0.1b d3         110 P8.26           227 P8.05
-P9.22	clk
+vin 0.1b d4         109 P8.15b          226 P8.24
 vin 0.1b d5         108 P9.16           225 P8.25
-P9.24	vsync
+vin 0.1b d6         107 P9.14           224 P8.20
-P9.26	hsync
+vin 0.1b d7         106 -               223 P8.21
-P9.41	de
+
 
-P9.12	d0	also available on P9.19
+                    ioset 1
-P9.11	d1	also available on P9.20 and P9.27
+vin 2.1a clk        166 P8.09
-P8.17	d2
+vin 2.1a de         170 P9.29b
-P8.27	d3
+vin 2.1a fld        169 P9.31b
-P8.28	d4 or fld
+vin 2.1a hsync      174 P9.17b
-P8.29	d5
+vin 2.1a vsync      173 P9.18b
-P8.30	d6
+vin 2.1a d8         188 P8.08
-P8.46	d7 or d17
+vin 2.1a d9         187 P8.07
-P8.37	d8 or d17
+vin 2.1a d10        186 P8.10
-P8.38	d9
+vin 2.1a d11        185 P9.42a
-P8.36	d10
+vin 2.1a d12        184 P9.28
-P8.34	d11	same pin as vin2b vsync, see comments there
+vin 2.1a d13        183 P9.30
-P8.35	d12
+vin 2.1a d14        182 P9.29a
-P8.33	d13
+vin 2.1a d15        181 P9.31a