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`timescale 1ns / 1ps
1		`timescale 1ns / 1ps
2		//////////////////////////////////////////////////////////////////////////////////
3		// Company:
4		// Engineer:
5		//
6		// Create Date: 22:50:18 01/24/2013
7		// Design Name:
8		// Module Name: Lab3_1
9		// Project Name:
10		// Target Devices:
11		// Tool versions:
12		// Description:
13		//
14		// Dependencies:
15		//
16		// Revision:
17		// Revision 0.01 - File Created
18		// Additional Comments:
19		//
20		//////////////////////////////////////////////////////////////////////////////////
21		module Lab3_1(
22		input clock,
23		output en_1,
24		output en_2,
25		output en_3,
26		output en_4,
27		output a,
28		output b,
29		output c,
30		output d,
31		output e,
32		output f,
33		output g
34		);
35
36		parameter MSB=24;
37
38		reg[MSB:0] count;
39		reg[MSB:0] count2;
40		reg[2:0] count3=3;
41
42		reg[1:0] pos;
43
44		reg[3:0] pstate;
45		reg[6:0] loop;
46
47		/*reg[6:0] id;
48		id[7] = 5;
49		id[6] = 4;
50		id[5] = 3;
51		id[4] = 0;
52		id[3] = 4;
53		id[2] = 7;
54		id[1] = 4;
55		id[0] = 5;*/
56
57		reg[3:0] number;
58
59		reg[3:0] en = 4'b1111;
60
61		assign en_1 = en[0];
62		assign en_2 = en[1];
63		assign en_3 = en[2];
64		assign en_4 = en[3];
65
66		segment num(number,a,b,c,d,e,f,g);
67
68		always@(posedge clock)
69		begin
70		if(count<=134217)
71		count <= count + 1;
72		else
73		count <= 1;
74		end
75
76		always@(posedge clock)
77		begin
78		if(count2<33554432)
79		count2 <= count2 + 1;
80		else begin
81		count2 <= 1;
82		count3 <= count3+1;
83		end
84		end
85
86		always@(posedge clock)
87		begin
88		if(loop == 99)
89		loop <= 0;
90		else
91		loop <= loop + 1;
92		end
93
94		//เลข
95		always@(posedge clock)
96		begin
97		if(count == 1)
98		begin
99		if(pstate == count3) begin
100		pstate <= count3-3;
101		end
102		else
103		pstate <= pstate + 1;
104		end
105		if(count2 == 1)
106		begin
107	-	pstate<=pstate-3;
107	+	pstate<=pstate-2;
108		end
109		end
110
111		//ตำแหน่ง
112		always@(posedge clock)
113		begin
114		if(count == 1)
115		pos <= pos + 1;
116		end
117
118		always@(*)
119		begin
120		case(pos)
121		0 : begin
122		en = 4'b0111;
123		end
124		1 : begin
125		en = 4'b1011;
126		end
127		2 : begin
128		en = 4'b1101;
129		end
130		3 : begin
131		en = 4'b1110;
132		end
133		endcase
134		end
135
136		always@(*)
137		begin
138		number = 0;
139
140		case(pstate)
141		0 : begin
142		number = 5;
143		end
144		1 : begin
145		number = 4;
146		end
147		2 : begin
148		number = 3;
149		end
150		3 : begin
151		number = 0;
152		end
153		4 : begin
154		number = 4;
155		end
156		5 : begin
157		number = 7;
158		end
159		6 : begin
160		number = 4;
161		end
162		7 : begin
163		number = 5;
164		end
165		endcase
166		end
167		endmodule