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| 1 | library IEEE; | |
| 2 | use IEEE.STD_LOGIC_1164.ALL; | |
| 3 | use IEEE.STD_LOGIC_ARITH.ALL; | |
| 4 | use IEEE.STD_LOGIC_UNSIGNED.ALL; | |
| 5 | ||
| 6 | entity MUX_2_1 is | |
| 7 | Port ( | |
| 8 | a,b,S : in std_logic; | |
| 9 | O : out std_logic; | |
| 10 | ) | |
| 11 | end MUX_2_1; | |
| 12 | ||
| 13 | architecture Behavioral of MUX_2_1 is | |
| 14 | begin | |
| 15 | - | if (S = '0' ) then |
| 15 | + | if S = '0' then |
| 16 | O <= a; | |
| 17 | else | |
| 18 | O <= b; | |
| 19 | end if; | |
| 20 | end Behavioral; |
