View difference between Paste ID: cjza1CnD and k0vTt5rT

 diff --git a/libmaple/i2c.c b/libmaple/i2c.c
-index 9c93d3f..2a98b79 100644
+index 9c93d3f..4902ec3 100644
 --- a/libmaple/i2c.c
 +++ b/libmaple/i2c.c
 @@ -154,6 +154,7 @@ void i2c_bus_reset(const i2c_dev *dev) {
  void i2c_init(i2c_dev *dev) {
      rcc_reset_dev(dev->clk_id);
      rcc_clk_enable(dev->clk_id);
 +    _i2c_irq_priority_fixup(dev);
  }
 
  /* Hack for deprecated bit of STM32F1 functionality */
-@@ -198,12 +199,26 @@ void i2c_master_enable(i2c_dev *dev, uint32 flags) {
+@@ -198,12 +199,30 @@ void i2c_master_enable(i2c_dev *dev, uint32 flags) {
      nvic_irq_enable(dev->er_nvic_line);
      i2c_enable_irq(dev, I2C_IRQ_EVENT | I2C_IRQ_BUFFER | I2C_IRQ_ERROR);
 
 +    /* Configure the slave unit */
 +    if (flags & I2C_SLAVE_DUAL_ADDRESS) {
 +		i2c_slave_dual_address_enable(dev);
 +	}
 +
 +	if (flags & I2C_SLAVE_GENERAL_CALL) {
 +		i2c_slave_general_call_enable(dev);
 +	}
 +
 +	/* store all of the flags */
 +	dev->config_flags = flags;
 +
      /* Make it go! */
      i2c_peripheral_enable(dev);
 +    i2c_enable_ack(dev);
 
      dev->state = I2C_STATE_IDLE;
  }
 
 +void i2c_slave_enable(i2c_dev *dev, uint32 flags) {
 +	i2c_disable(dev);
 +	i2c_master_enable(dev, dev->config_flags | flags);
 +}
-@@ -303,149 +318,297 @@ void _i2c_irq_handler(i2c_dev *dev) {
+
  /**
   * @brief Process an i2c transaction.
   *
 @@ -303,150 +322,296 @@ void _i2c_irq_handler(i2c_dev *dev) {
       */
      dev->timestamp = systick_uptime();
 
 -    /*
 -     * EV5: Start condition sent
 +    /* Add Slave support
 +     * Barry Carter 2012
 +     * [email protected]
       */
 -    if (sr1 & I2C_SR1_SB) {
 -        msg->xferred = 0;
 -        i2c_enable_irq(dev, I2C_IRQ_BUFFER);
 -
 -        /*
 -         * Master receiver
 -         */
 -        if (read) {
 -            i2c_enable_ack(dev);
 +
 +    /* Check to see if MSL master slave bit is set */
 +    if ((sr2 & I2C_SR2_MSL) != I2C_SR2_MSL) { /* 0 = slave mode 1 = master */
 +
 +    	dev->state = I2C_STATE_BUSY;
 +
 +        /* Check for address match */
 +        if (sr1 & I2C_SR1_ADDR) {
 +        	/* Find out which address was matched */
 +        	/* Check the general call address first */
 +        	if (sr2 & I2C_SR2_GENCALL) {
 +        		dev->i2c_slave_msg->addr = 0;
 +        	}
 +        	/* We matched the secondary address */
 +        	else if (sr2 & I2C_SR2_DUALF) {
 +        		dev->i2c_slave_msg->addr = dev->regs->OAR2 & 0xFE;
 +        	}
 +        	/* We matched the primary address */
 +        	else if ((sr2 & I2C_SR2_DUALF) != I2C_SR2_DUALF) {
 +        		dev->i2c_slave_msg->addr = dev->regs->OAR1 & 0xFE;
 +        	}
 +        	/* Shouldn't get here */
 +        	else {
 +        		dev->i2c_slave_msg->addr = -1; /* uh oh */
 +        	}
 +
 +        	/* if we have buffered io */
 +        	if ((dev->config_flags & I2C_SLAVE_USE_RX_BUFFER) ||
 +        		(dev->config_flags & I2C_SLAVE_USE_TX_BUFFER)) {
 +
 +        		/* if receiving then this would be a repeated start
 +        		 *
 +        		 *if we have some bytes already
 +        		 */
 +				if (((sr1 & I2C_SR1_TXE) != I2C_SR1_TXE) &&
 +					(dev->i2c_slave_msg->xferred > 0)  &&
 +					(dev->config_flags & I2C_SLAVE_USE_RX_BUFFER)) {
 +					/* Call the callback with the contents of the data */
 +					if (dev->i2c_slave_recv_callback != NULL) {
 +						(*(dev->i2c_slave_recv_callback))(dev->i2c_slave_msg);
 +					}
 +				}
 +
 +				/* Reset the message back to defaults.
 +				 * We are starting a new message
 +				 */
 +				dev->i2c_slave_msg->flags = 0;
 +				dev->i2c_slave_msg->length = 0;
 +				dev->i2c_slave_msg->xferred = 0;
 +				dev->msgs_left = 0;
 +				dev->timestamp = systick_uptime();
 +
 +				/* We have been addressed with SLA+R so
 +				 * the master wants us to transmit
 +				 */
 +        	    if ((sr1 & I2C_SR1_TXE) &&
 +					(dev->config_flags & I2C_SLAVE_USE_TX_BUFFER)) {
 +        	    	/* Call the transmit callback so it can populate the msg
 +        	    	 * data with the bytes to go
 +        	    	 */
 +        	    	if (dev->i2c_slave_transmit_callback != NULL) {
 +        	    		(*(dev->i2c_slave_transmit_callback))(dev->i2c_slave_msg);
 +        	    	}
 +				}
 +			}
 +
 +            sr1 = sr2 = 0;
 +        }
 +
 +         /* EV3: Master requesting data from slave. Transmit a byte*/
 +        if (sr1 & I2C_SR1_TXE) {
 +        	if (dev->config_flags & I2C_SLAVE_USE_TX_BUFFER) {
 +        		if (dev->i2c_slave_msg->xferred >= dev->i2c_slave_msg->length) {
 +        			/* End of the transmit buffer? If so we NACK */
 +        			i2c_disable_ack(dev);
 +        			/* We have to either issue a STOP or write something here.
 +        			 * STOP here seems to screw up some masters,
 +					 * For now padding with 0
 +        			 */
 +        			i2c_write(dev, 0);
 +        			/*i2c_stop_condition(dev); // This is causing bus lockups way more than it should !? Seems some I2C master devices freak out here*/
 +        		}
 +        		else
 +        		{
 +        			/* NACk the last byte */
 +					if (dev->i2c_slave_msg->xferred == dev->i2c_slave_msg->length-1) {
 +						i2c_disable_ack(dev);
 +					}
 +					else {
 +						i2c_enable_ack(dev);
 +					}
 +					i2c_write(dev, dev->i2c_slave_msg->data[dev->i2c_slave_msg->xferred++]);
 +        		}
 +        	}
 +        	else
 +        	{
 +				/* Call the callback to get the data we need.
 +				 * The callback is expected to write using i2c_write(...)
 +				 * If the slave is going to terminate the transfer, this function should
 +				 * also do a NACK on the last byte!
 +				 */
 +				if (dev->i2c_slave_transmit_callback != NULL) (*(dev->i2c_slave_transmit_callback))(dev->i2c_slave_msg);
 +        	}
 +
 +        	sr1 = sr2 = 0;
 +        }
 +
 +        /* EV2: Slave received data from a master. Get from DR */
 +        if (sr1 & I2C_SR1_RXNE) {
 +        	if (dev->config_flags & I2C_SLAVE_USE_RX_BUFFER) {
 +        		/* Fill the buffer with the contents of the data register */
 +         		dev->i2c_slave_msg->data[dev->i2c_slave_msg->xferred++] = dev->regs->DR;
 +        		dev->i2c_slave_msg->length++;
 +        	}
 +        	else  {
 +        		/* Call the callback with the contents of the data */
 +        		dev->i2c_slave_msg->data[0] = dev->regs->DR;
 +        		if (dev->i2c_slave_recv_callback != NULL) (*(dev->i2c_slave_recv_callback))(dev->i2c_slave_msg);
 +        	}
 +            sr1 = sr2 = 0;
          }
 
 -        i2c_send_slave_addr(dev, msg->addr, read);
 -        sr1 = sr2 = 0;
 -    }
 +        /* EV4: Slave has detected a STOP condition on the bus */
 +        if (sr1 & I2C_SR1_STOPF) {
 +            dev->regs->CR1 |= I2C_CR1_PE;
 
 -    /*
 -     * EV6: Slave address sent
 -     */
 -    if (sr1 & I2C_SR1_ADDR) {
 -        /*
 -         * Special case event EV6_1 for master receiver.
 -         * Generate NACK and restart/stop condition after ADDR
 -         * is cleared.
 -         */
 -        if (read) {
 -            if (msg->length == 1) {
 -                i2c_disable_ack(dev);
 -                if (dev->msgs_left > 1) {
 -                    i2c_start_condition(dev);
 -                    I2C_CRUMB(RX_ADDR_START, 0, 0);
 -                } else {
 -                    i2c_stop_condition(dev);
 -                    I2C_CRUMB(RX_ADDR_STOP, 0, 0);
 -                }
 -            }
 -        } else {
 -            /*
 -             * Master transmitter: write first byte to fill shift
 -             * register.  We should get another TXE interrupt
 -             * immediately to fill DR again.
 -             */
 -            if (msg->length != 1) {
 -                i2c_write(dev, msg->data[msg->xferred++]);
 -            }
-+            	(dev->config_flags & I2C_SLAVE_USE_RX_BUFFER)) {
+
 -        sr1 = sr2 = 0;
 -    }
 +            if ((dev->config_flags & I2C_SLAVE_USE_RX_BUFFER) ||
 +            	(dev->config_flags & I2C_SLAVE_USE_TX_BUFFER)) {
 
 -    /*
 -     * EV8: Master transmitter
 -     * Transmit buffer empty, but we haven't finished transmitting the last
 -     * byte written.
 -     */
 -    if ((sr1 & I2C_SR1_TXE) && !(sr1 & I2C_SR1_BTF)) {
 -        I2C_CRUMB(TXE_ONLY, 0, 0);
 -        if (dev->msgs_left) {
 -            i2c_write(dev, msg->data[msg->xferred++]);
 -            if (msg->xferred == msg->length) {
 -                /*
 -                 * End of this message. Turn off TXE/RXNE and wait for
 -                 * BTF to send repeated start or stop condition.
 -                 */
 -                i2c_disable_irq(dev, I2C_IRQ_BUFFER);
 -                dev->msgs_left--;
 -            }
 -        } else {
 -            /*
 -             * This should be impossible...
 -             */
 -            ASSERT(0);
-+        		 * This is handled in the error IRQ
+
 -        sr1 = sr2 = 0;
 -    }
 +        		/* The callback with the data will happen on a NACK of the last data byte.
 +        		 * This is handled in the error IRQ (AF bit)
 +        		 */
 +        	}
 
 -    /*
 -     * EV8_2: Master transmitter
 -     * Last byte sent, program repeated start/stop
 -     */
 -    if ((sr1 & I2C_SR1_TXE) && (sr1 & I2C_SR1_BTF)) {
 -        I2C_CRUMB(TXE_BTF, 0, 0);
 -        if (dev->msgs_left) {
 -            I2C_CRUMB(TEST, 0, 0);
 -            /*
 -             * Repeated start insanity: We can't disable ITEVTEN or else SB
 -             * won't interrupt, but if we don't disable ITEVTEN, BTF will
 -             * continually interrupt us. What the fuck ST?
 -             */
 -            i2c_start_condition(dev);
 -            while (!(dev->regs->SR1 & I2C_SR1_SB))
 -                ;
 -            dev->msg++;
 -        } else {
 -            i2c_stop_condition(dev);
 -
 -            /*
 -             * Turn off event interrupts to keep BTF from firing until
 -             * the end of the stop condition. Why on earth they didn't
 -             * have a start/stop condition request clear BTF is beyond
 -             * me.
 -             */
 -            i2c_disable_irq(dev, I2C_IRQ_EVENT);
 -            I2C_CRUMB(STOP_SENT, 0, 0);
 -            dev->state = I2C_STATE_XFER_DONE;
 +            sr1 = sr2 = 0;
 +            dev->state = I2C_STATE_IDLE;
          }
 -        sr1 = sr2 = 0;
 -    }
 
 -    /*
 -     * EV7: Master Receiver
 -     */
 -    if (sr1 & I2C_SR1_RXNE) {
 -        I2C_CRUMB(RXNE_ONLY, 0, 0);
 -        msg->data[msg->xferred++] = dev->regs->DR;
 -
 -        /*
 -         * EV7_1: Second to last byte in the reception? Set NACK and generate
 -         * stop/restart condition in time for the last byte. We'll get one more
 -         * RXNE interrupt before shutting things down.
 -         */
 -        if (msg->xferred == (msg->length - 1)) {
 -            i2c_disable_ack(dev);
 -            if (dev->msgs_left > 2) {
 -                i2c_start_condition(dev);
 -                I2C_CRUMB(RXNE_START_SENT, 0, 0);
 -            } else {
 -                i2c_stop_condition(dev);
 -                I2C_CRUMB(RXNE_STOP_SENT, 0, 0);
 -            }
 -        } else if (msg->xferred == msg->length) {
 -            dev->msgs_left--;
 -            if (dev->msgs_left == 0) {
 -                /*
 -                 * We're done.
 -                 */
 -                I2C_CRUMB(RXNE_DONE, 0, 0);
 -                dev->state = I2C_STATE_XFER_DONE;
 -            } else {
 -                dev->msg++;
 -            }
-+    /* Process the master code */
+
-+    /*if ((sr2 & I2C_SR2_MSL) == I2C_SR2_MSL)*/ { /* 0 = slave mode 1 = master */
+
      }
-+		 * EV5: Start condition sent
+
 +	/*
-+		if (sr1 & I2C_SR1_SB) {
++	 * EV5: Start condition sent
-+			msg->xferred = 0;
++	 */
-+			i2c_enable_irq(dev, I2C_IRQ_BUFFER);
++	if (sr1 & I2C_SR1_SB) {
 +		msg->xferred = 0;
 +		i2c_enable_irq(dev, I2C_IRQ_BUFFER);
-+			 * Master receiver
+
 +		/*
-+			if (read) {
++		 * Master receiver
-+				i2c_enable_ack(dev);
+
 +		if (read) {
 +			i2c_enable_ack(dev);
-+			i2c_send_slave_addr(dev, msg->addr, read);
+
-+			sr1 = sr2 = 0;
+
 +		i2c_send_slave_addr(dev, msg->addr, read);
 +		sr1 = sr2 = 0;
 +	}
-+		 * EV6: Slave address sent
+
 +	/*
-+		if (sr1 & I2C_SR1_ADDR) {
++	 * EV6: Slave address sent
 +	 */
-+			 * Special case event EV6_1 for master receiver.
++	if (sr1 & I2C_SR1_ADDR) {
-+			 * Generate NACK and restart/stop condition after ADDR
+
-+			 * is cleared.
++		 * Special case event EV6_1 for master receiver.
 +		 * Generate NACK and restart/stop condition after ADDR
-+			if (read) {
++		 * is cleared.
-+				if (msg->length == 1) {
+
-+					i2c_disable_ack(dev);
++		if (read) {
-+					if (dev->msgs_left > 1) {
++			if (msg->length == 1) {
-+						i2c_start_condition(dev);
+
-+						I2C_CRUMB(RX_ADDR_START, 0, 0);
++				if (dev->msgs_left > 1) {
-+					} else {
+
-+						i2c_stop_condition(dev);
++					I2C_CRUMB(RX_ADDR_START, 0, 0);
-+						I2C_CRUMB(RX_ADDR_STOP, 0, 0);
+
 +					i2c_stop_condition(dev);
 +					I2C_CRUMB(RX_ADDR_STOP, 0, 0);
 +				}
 +			}
-+				 * Master transmitter: write first byte to fill shift
++		} else {
-+				 * register.  We should get another TXE interrupt
+
-+				 * immediately to fill DR again.
++			 * Master transmitter: write first byte to fill shift
 +			 * register.  We should get another TXE interrupt
-+				if (msg->length != 1) {
++			 * immediately to fill DR again.
-+					i2c_write(dev, msg->data[msg->xferred++]);
+
 +			if (msg->length != 1) {
 +				i2c_write(dev, msg->data[msg->xferred++]);
-+			sr1 = sr2 = 0;
+
 +		}
 +		sr1 = sr2 = 0;
 +	}
-+		 * EV8: Master transmitter
+
-+		 * Transmit buffer empty, but we haven't finished transmitting the last
++	/*
-+		 * byte written.
++	 * EV8: Master transmitter
 +	 * Transmit buffer empty, but we haven't finished transmitting the last
-+		if ((sr1 & I2C_SR1_TXE) && !(sr1 & I2C_SR1_BTF)) {
++	 * byte written.
-+			I2C_CRUMB(TXE_ONLY, 0, 0);
++	 */
-+			if (dev->msgs_left) {
++	if ((sr1 & I2C_SR1_TXE) && !(sr1 & I2C_SR1_BTF)) {
 +		I2C_CRUMB(TXE_ONLY, 0, 0);
-+				if (msg->xferred == msg->length) {
++		if (dev->msgs_left) {
-+					/*
++			i2c_write(dev, msg->data[msg->xferred++]);
-+					 * End of this message. Turn off TXE/RXNE and wait for
++			if (msg->xferred == msg->length) {
-+					 * BTF to send repeated start or stop condition.
+
-+					 */
++				 * End of this message. Turn off TXE/RXNE and wait for
-+					i2c_disable_irq(dev, I2C_IRQ_BUFFER);
++				 * BTF to send repeated start or stop condition.
-+					dev->msgs_left--;
+
 +				i2c_disable_irq(dev, I2C_IRQ_BUFFER);
 +				dev->msgs_left--;
 +			}
-+				 * This should be impossible...
++		} else {
 +			/*
-+				ASSERT(0);
++			 * This should be impossible...
 +			 */
-+			sr1 = sr2 = 0;
++			ASSERT(0);
 +		}
 +		sr1 = sr2 = 0;
 +	}
-+		 * EV8_2: Master transmitter
+
-+		 * Last byte sent, program repeated start/stop
++	/*
 +	 * EV8_2: Master transmitter
-+		if ((sr1 & I2C_SR1_TXE) && (sr1 & I2C_SR1_BTF)) {
++	 * Last byte sent, program repeated start/stop
-+			I2C_CRUMB(TXE_BTF, 0, 0);
++	 */
-+			if (dev->msgs_left) {
++	if ((sr1 & I2C_SR1_TXE) && (sr1 & I2C_SR1_BTF)) {
-+				I2C_CRUMB(TEST, 0, 0);
++		I2C_CRUMB(TXE_BTF, 0, 0);
 +		if (dev->msgs_left) {
-+				 * Repeated start insanity: We can't disable ITEVTEN or else SB
++			I2C_CRUMB(TEST, 0, 0);
-+				 * won't interrupt, but if we don't disable ITEVTEN, BTF will
+
-+				 * continually interrupt us. What the fuck ST?
++			 * Repeated start insanity: We can't disable ITEVTEN or else SB
 +			 * won't interrupt, but if we don't disable ITEVTEN, BTF will
 +			 * continually interrupt us. What the fuck ST?
-+				while (!(dev->regs->SR1 & I2C_SR1_SB))
+
-+					;
++			i2c_start_condition(dev);
 +			while (!(dev->regs->SR1 & I2C_SR1_SB))
 +				;
 +			dev->msg++;
 +		} else {
 +			i2c_stop_condition(dev);
-+				 * Turn off event interrupts to keep BTF from firing until
+
-+				 * the end of the stop condition. Why on earth they didn't
+
-+				 * have a start/stop condition request clear BTF is beyond
++			 * Turn off event interrupts to keep BTF from firing until
-+				 * me.
++			 * the end of the stop condition. Why on earth they didn't
 +			 * have a start/stop condition request clear BTF is beyond
-+				i2c_disable_irq(dev, I2C_IRQ_EVENT);
++			 * me.
-+				I2C_CRUMB(STOP_SENT, 0, 0);
+
 +			i2c_disable_irq(dev, I2C_IRQ_EVENT);
 +			I2C_CRUMB(STOP_SENT, 0, 0);
-+			sr1 = sr2 = 0;
++			dev->state = I2C_STATE_XFER_DONE;
 +		}
 +		sr1 = sr2 = 0;
 +	}
-+		 * EV7: Master Receiver
+
 +	/*
-+		if (sr1 & I2C_SR1_RXNE) {
++	 * EV7: Master Receiver
-+			I2C_CRUMB(RXNE_ONLY, 0, 0);
++	 */
-+			msg->data[msg->xferred++] = dev->regs->DR;
++	if (sr1 & I2C_SR1_RXNE) {
 +		I2C_CRUMB(RXNE_ONLY, 0, 0);
 +		msg->data[msg->xferred++] = dev->regs->DR;
-+			 * EV7_1: Second to last byte in the reception? Set NACK and generate
+
-+			 * stop/restart condition in time for the last byte. We'll get one more
+
-+			 * RXNE interrupt before shutting things down.
++		 * EV7_1: Second to last byte in the reception? Set NACK and generate
 +		 * stop/restart condition in time for the last byte. We'll get one more
-+			if (msg->xferred == (msg->length - 1)) {
++		 * RXNE interrupt before shutting things down.
 +		 */
-+				if (dev->msgs_left > 2) {
++		if (msg->xferred == (msg->length - 1)) {
 +			i2c_disable_ack(dev);
-+					I2C_CRUMB(RXNE_START_SENT, 0, 0);
++			if (dev->msgs_left > 2) {
 +				i2c_start_condition(dev);
 +				I2C_CRUMB(RXNE_START_SENT, 0, 0);
-+					I2C_CRUMB(RXNE_STOP_SENT, 0, 0);
+
 +				i2c_stop_condition(dev);
-+			} else if (msg->xferred == msg->length) {
++				I2C_CRUMB(RXNE_STOP_SENT, 0, 0);
 +			}
-+				if (dev->msgs_left == 0) {
++		} else if (msg->xferred == msg->length) {
-+					/*
++			dev->msgs_left--;
-+					 * We're done.
++			if (dev->msgs_left == 0) {
-+					 */
+
-+					I2C_CRUMB(RXNE_DONE, 0, 0);
++				 * We're done.
-+					dev->state = I2C_STATE_XFER_DONE;
+
 +				I2C_CRUMB(RXNE_DONE, 0, 0);
-+					dev->msg++;
+
 +			} else {
 +				dev->msg++;
 +			}
 +		}
 +	}
 +
-@@ -456,10 +619,46 @@ void _i2c_irq_handler(i2c_dev *dev) {
+
 
  /*
 @@ -456,10 +621,46 @@ void _i2c_irq_handler(i2c_dev *dev) {
  void _i2c_irq_error_handler(i2c_dev *dev) {
      I2C_CRUMB(ERROR_ENTRY, dev->regs->SR1, dev->regs->SR2);
 
 -    dev->error_flags = dev->regs->SR2 & (I2C_SR1_BERR |
 +    dev->error_flags = dev->regs->SR1 & (I2C_SR1_BERR |
                                           I2C_SR1_ARLO |
                                           I2C_SR1_AF |
                                           I2C_SR1_OVR);
 +
 +    /* Are we in slave mode? */
 +    if ((dev->regs->SR2 & I2C_SR2_MSL) != I2C_SR2_MSL) {
 +    	/* Check to see if the master device did a NAK on the last bit
 +    	 * This is perfectly valid for a master to do this on the bus.
 +    	 * We ignore this. Any further error processing takes us into dead
 +    	 * loop waiting for the stop condition that will never arrive
 +    	 */
 +    	if (dev->regs->SR1 & I2C_SR1_AF) {
 +    	    /* Clear flags */
 +    	    dev->regs->SR1 = 0;
 +    	    dev->regs->SR2 = 0;
 +    	    /* We need to write something to CR1 to clear the flag.
 +    	     * This isn't really mentioned but seems important */
 +    	    i2c_enable_ack(dev);
 +    	    dev->state = I2C_STATE_IDLE;
 +
 +    	    if (dev->config_flags & I2C_SLAVE_USE_RX_BUFFER && dev->i2c_slave_msg->xferred > 0) {
 +				/* Call the callback with the contents of the data */
 +				if (dev->i2c_slave_recv_callback != NULL) (*(dev->i2c_slave_recv_callback))(dev->i2c_slave_msg);
 +			}
 +    	    return;
 +    	}
 +    	/* Catch any other strange errors while in slave mode.
 +    	 * I have seen BERR caused by an over fast master device
 +    	 * as well as several overflows and arbitration failures.
 +    	 * We are going to reset SR flags and carry on at this point which
 +    	 * is not the best thing to do, but stops the bus locking up completely
 +    	 * If we carry on below and send the stop bit, the code spins forever */
 +        /* Clear flags */
 +        dev->regs->SR1 = 0;
 +        dev->regs->SR2 = 0;
 +        dev->state = I2C_STATE_IDLE;
 +		return;
 +    }
 +
-@@ -507,3 +706,31 @@ static void set_ccr_trise(i2c_dev *dev, uint32 flags) {
+
      dev->regs->SR1 = 0;
      dev->regs->SR2 = 0;
 @@ -507,3 +708,31 @@ static void set_ccr_trise(i2c_dev *dev, uint32 flags) {
      i2c_set_clk_control(dev, ccr);
      i2c_set_trise(dev, trise);
  }
 +
 +
 +/**
 + * @brief callback for when the device acts as a slave. If using an rx buffer, this is triggered
 + * after the last byte, otherwise it is called for every incoming packet.
 + * @param dev I2C device
 + * @param msg The dev_msg to pass to the slave init code
 + * @param func The function pointer to call
 + */
 +void i2c_slave_attach_recv_handler(i2c_dev *dev, i2c_msg *msg, i2c_slave_recv_callback_func func) {
 +    dev->i2c_slave_recv_callback = func;
 +    dev->i2c_slave_msg = msg;
 +    msg->xferred = 0;
 +}
 +
 +
 +/**
 + * @brief callback for when the device acts as a slave. If using a tx buffer, this is triggered
 + * after the device is successsfully addressed with SLA+R.
 + * @param dev I2C device
 + * @param msg The dev_msg to pass to the slave init code
 + * @param func The function pointer to call
 + */
 +void i2c_slave_attach_transmit_handler(i2c_dev *dev, i2c_msg *msg, i2c_slave_transmit_callback_func func) {
 +	dev->i2c_slave_transmit_callback = func;
-diff --git a/libmaple/i2c_private.h b/libmaple/i2c_private.h
+
-index 5b79516..7d25ae4 100644
+
---- a/libmaple/i2c_private.h
+
-+++ b/libmaple/i2c_private.h
+
-@@ -76,4 +76,5 @@ static inline struct gpio_dev* sda_port(const i2c_dev *dev) {
+index ff1c313..d4eac61 100644
-  * i2c_master_enable(). */
+
- void _i2c_set_ccr_trise(i2c_dev *dev, uint32 flags);
+
 @@ -93,6 +93,7 @@ typedef struct i2c_msg {
 
- #endif  /* _LIBMAPLE_I2C_PRIVATE_H_ */
+
  #define I2C_MSG_10BIT_ADDR      0x2
-index ff1c313..146c880 100644
+
      /**
       * Bitwise OR of:
       * - I2C_MSG_READ (write is default)
 @@ -197,6 +198,10 @@ typedef struct i2c_msg {
  #define I2C_DUTY_16_9           0x2           // 16/9 duty ratio
  /* Flag 0x4 is reserved; DO NOT USE. */
  #define I2C_BUS_RESET           0x8           // Perform a bus reset
 +#define I2C_SLAVE_USE_RX_BUFFER 0x10          // Use a buffered message when doing a slave recv
 +#define I2C_SLAVE_USE_TX_BUFFER 0x20          // Use a buffered message when doing a slave transmit
 +#define I2C_SLAVE_DUAL_ADDRESS  0x40          // Enable the dual slave address scheme
 +#define I2C_SLAVE_GENERAL_CALL  0x80          // Enable the dual slave address scheme
  void i2c_master_enable(i2c_dev *dev, uint32 flags);
 
  #define I2C_ERROR_PROTOCOL      (-1)
-+#define I2C_SLAVE_USE_RX_BUFFER	 0x10		   // Use a buffered message when doing a slave recv
+
-+#define I2C_SLAVE_USE_TX_BUFFER	 0x20		   // Use a buffered message when doing a slave transmit
+
-+#define I2C_SLAVE_DUAL_ADDRESS	 0x40		   // Enable the dual slave address scheme
+
-+#define I2C_SLAVE_GENERAL_CALL	 0x80		   // Enable the dual slave address scheme
+
 +/* Barry Carter
 + * Slave support
 + */
 +
 +/**
 + * @brief Enable Dual addressing mode to allow peripheral to have 2 addresses
 + * @param dev I2C device
 +  */
 +static inline void i2c_slave_dual_address_enable(i2c_dev *dev) {
 +    dev->regs->OAR2 |= I2C_OAR2_ENDUAL;
 +}
 +
 +/**
 + * @brief Enable General Call to allow the  unit to respond on addr 0x00
 + * @param dev I2C device
 +  */
 +static inline void i2c_slave_general_call_enable(i2c_dev *dev) {
 +    dev->regs->CR1 |= I2C_CR1_ENGC;
 +}
 +
 +/* callback functions */
 +/* Callback handler for data received over the bus */
 +void i2c_slave_attach_recv_handler(i2c_dev *dev, i2c_msg *msg, i2c_slave_recv_callback_func func);
 +
 +/* Callback handler for data being requested over the bus
 + * The callback function must call i2c_write to get the data over the bus
 + */
 +void i2c_slave_attach_transmit_handler(i2c_dev *dev, i2c_msg *msg, i2c_slave_transmit_callback_func func);
 +
 +/**
 + * @brief Set the primary I2c slave address
 + * @param dev I2C device
 + * @param address the 8 or 10 bit i2c address
 +  */
 +static inline void i2c_slave_set_own_address(i2c_dev *dev, uint16 address) {
 +    dev->regs->OAR1 = address <<1;
 +}
 +
 +/**
 + * @brief Set the secondary I2c slave address
 + * @param dev I2C device
 + * @param address the 8 or 10 bit i2c address
 +  */
 +static inline void i2c_slave_set_own_address2(i2c_dev *dev, uint16 address) {
 +dev->regs->OAR2 = (address <<1 ) | I2C_OAR2_ENDUAL;
 +}
 +
  #ifdef __cplusplus
  }
  #endif
 diff --git a/libmaple/include/libmaple/i2c_common.h b/libmaple/include/libmaple/i2c_common.h
-+	dev->regs->OAR2 = (address <<1 ) | I2C_OAR2_ENDUAL;
+index 17cabe3..a855d4b 100644
 --- a/libmaple/include/libmaple/i2c_common.h
 +++ b/libmaple/include/libmaple/i2c_common.h
 @@ -55,6 +55,8 @@ typedef enum i2c_state {
      I2C_STATE_ERROR             = -1 /**< Error occurred */
  } i2c_state;
 
-index 17cabe3..7337240 100644
+
 +typedef void (*i2c_slave_transmit_callback_func)(struct i2c_msg *);
  /**
   * @brief I2C device type.
   */
 @@ -88,6 +90,17 @@ typedef struct i2c_dev {
      nvic_irq_num ev_nvic_line;  /**< Event IRQ number */
      nvic_irq_num er_nvic_line;  /**< Error IRQ number */
      volatile i2c_state state;   /**< Device state */
 +    uint32 config_flags;        /**< Configuration flags */
 +
 +    /* Barry Carter
 +     * Slave implementation. Callback functions in this struct allow
 +     * for a separate callback function for each I2C unit available onboard
 +     */
 +    i2c_slave_transmit_callback_func i2c_slave_transmit_callback;
-+    uint32 config_flags;		/**< Configuration flags */
+
 +
 +    struct i2c_msg *i2c_slave_msg; /* the message that the i2c slave will use */
 +
  } i2c_dev;
 
  #endif