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| 1 | ||
| 2 | library IEEE; | |
| 3 | use IEEE.STD_LOGIC_1164.all; | |
| 4 | use IEEE.STD_LOGIC_ARITH.all; | |
| 5 | use IEEE.STD_LOGIC_UNSIGNED.all; | |
| 6 | ||
| 7 | - | entity CodeROM is |
| 7 | + | entity DataRAM is |
| 8 | Generic( | |
| 9 | - | n:integer := 11; -- code word size |
| 9 | + | n:integer := 8; -- data word size |
| 10 | - | m:integer := 127; -- ROM length |
| 10 | + | m:integer := 64; -- RAM length |
| 11 | - | k:integer := 7); -- adress bus size |
| 11 | + | k:integer := 6); -- adress bus size |
| 12 | Port( | |
| 13 | - | Code_Read: in std_logic; |
| 13 | + | Data_Read: in std_logic; |
| 14 | - | Code_Adr: in std_logic_vector(k-1 downto 0); |
| 14 | + | Data_Adr: in std_logic_vector(k-1 downto 0); |
| 15 | - | Code_Out: out std_logic_vector(n-1 downto 0)); |
| 15 | + | Data_In: in std_logic_vector(n-1 downto 0); |
| 16 | - | end CodeROM; |
| 16 | + | Data_Out: out std_logic_vector(n-1 downto 0)); |
| 17 | end DataRAM; | |
| 18 | - | architecture CodeROM_arch of CodeROM is |
| 18 | + | |
| 19 | - | subtype ROM_WORD is std_logic_vector(n-1 downto 0); |
| 19 | + | architecture DataRAM_arch of DataRAM is |
| 20 | - | type ROM_TYPE is array(0 to m-1) of ROM_WORD; |
| 20 | + | subtype RAM_WORD is std_logic_vector(n-1 downto 0); |
| 21 | - | signal Rom: ROM_TYPE := ( |
| 21 | + | type RAM_TYPE is array(0 to m-1) of RAM_WORD; |
| 22 | - | "00000000000", -- push width |
| 22 | + | signal Ram: RAM_TYPE := ( |
| 23 | - | "00000000001", -- push height |
| 23 | + | "00000100", -- var width 0 |
| 24 | - | "01110000000", -- mul |
| 24 | + | "00000101", -- var height 1 |
| 25 | - | "00000000000", -- push width |
| 25 | + | "00010100", -- var source 2 |
| 26 | - | "10000000000", -- sub |
| 26 | + | "00101000", -- var dest 3 |
| 27 | - | "00010000001", -- pushc 1 |
| 27 | + | "00000000", -- var i |
| 28 | - | "10000000000", -- sub |
| 28 | + | "00000000", -- var maxI |
| 29 | - | "00110000101", -- pop maxI |
| 29 | + | "00000000", -- var destAdr |
| 30 | - | "00000000000", -- push width |
| 30 | + | "00000000", -- var topL |
| 31 | - | "00010000001", -- pushc 1 |
| 31 | + | "00000000", -- var top |
| 32 | - | "01010000000", -- add |
| 32 | + | "00000000", -- var topR |
| 33 | - | "00110000100", -- pop i |
| 33 | + | "00000000", -- var left |
| 34 | - | "00000000010", -- push source |
| 34 | + | "00000000", -- var right |
| 35 | - | "00110000111", -- pop topL |
| 35 | + | "00000000", -- var botL |
| 36 | - | "00000000010", -- push source |
| 36 | + | "00000000", -- var bot |
| 37 | - | "00010000001", -- pushc 1 |
| 37 | + | "00000000", -- var botR |
| 38 | - | "01100000000", -- addk |
| 38 | + | "00000000", |
| 39 | - | "00110001000", -- pop top |
| 39 | + | "00000000", |
| 40 | - | "00010000010", -- pushc 2 |
| 40 | + | "00000000", |
| 41 | - | "01100000000", -- addk |
| 41 | + | "00000000", |
| 42 | - | "00110001001", -- pop topR |
| 42 | + | "00000000", |
| 43 | - | "00000000000", -- push width |
| 43 | + | "11111111", -- var source 20 |
| 44 | - | "01100000000", -- addk |
| 44 | + | "11111111", |
| 45 | - | "00110001010", -- pop left |
| 45 | + | "11111111", |
| 46 | - | "00000000000", -- push width |
| 46 | + | "11111111", |
| 47 | - | "01100000000", -- addk |
| 47 | + | "00011111", |
| 48 | - | "00010000010", -- pushc 2 |
| 48 | + | "10110110", |
| 49 | - | "01010000000", -- add |
| 49 | + | "11111111", |
| 50 | - | "00110001011", -- pop right |
| 50 | + | "11111111", |
| 51 | - | "00000000000", -- push width |
| 51 | + | "00000000", |
| 52 | - | "00010000010", -- pushc 2 |
| 52 | + | "00001111", |
| 53 | - | "01110000000", -- mul |
| 53 | + | "10110110", |
| 54 | - | "01100000000", -- addk |
| 54 | + | "11111111", |
| 55 | - | "00110001100", -- pop botL |
| 55 | + | "00000000", |
| 56 | - | "00000000000", -- push width |
| 56 | + | "00000000", |
| 57 | - | "00010000010", -- pushc 2 |
| 57 | + | "00011111", |
| 58 | - | "01110000000", -- mul |
| 58 | + | "11111111", |
| 59 | - | "01100000000", -- addk |
| 59 | + | "00000000", |
| 60 | - | "00010000001", -- pushc 1 |
| 60 | + | "00000000", |
| 61 | - | "01010000000", -- add |
| 61 | + | "00010001", |
| 62 | - | "00110001101", -- pop bot |
| 62 | + | "10101000", |
| 63 | - | "00000000000", -- push width |
| 63 | + | "00000000", -- var dest 40 |
| 64 | - | "00010000010", -- pushc 2 |
| 64 | + | "00000000", |
| 65 | - | "01110000000", -- mul |
| 65 | + | "00000000", |
| 66 | - | "01010000000", -- add |
| 66 | + | "00000000", |
| 67 | - | "00010000010", -- pushc 2 |
| 67 | + | "00000000", |
| 68 | - | "01010000000", -- add |
| 68 | + | "00000000", |
| 69 | - | "00110001110", -- pop botR |
| 69 | + | "00000000", |
| 70 | - | "00000000011", -- push dest |
| 70 | + | "00000000", |
| 71 | - | "00000000100", -- push i |
| 71 | + | "00000000", |
| 72 | - | "01010000000", -- add |
| 72 | + | "00000000", |
| 73 | - | "00110000110", -- pop destAdr |
| 73 | + | "00000000", |
| 74 | - | "00100000111", -- pushr topL |
| 74 | + | "00000000", |
| 75 | - | "00100001001", -- pushr topR |
| 75 | + | "00000000", |
| 76 | - | "10000000000", -- sub |
| 76 | + | "00000000", |
| 77 | - | "00100001010", -- pushr left |
| 77 | + | "00000000", |
| 78 | - | "00010000010", -- pushc 2 |
| 78 | + | "00000000", |
| 79 | - | "01110000000", -- mul |
| 79 | + | "00000000", |
| 80 | - | "01010000000", -- add |
| 80 | + | "00000000", |
| 81 | - | "00100001011", -- pushr right |
| 81 | + | "00000000", |
| 82 | - | "00010000010", -- pushc 2 |
| 82 | + | "00000000", |
| 83 | - | "01110000000", -- mul |
| 83 | + | "00000000", |
| 84 | - | "10000000000", -- sub |
| 84 | + | "00000000", |
| 85 | - | "00100001100", -- pushr botL |
| 85 | + | "00000000", |
| 86 | - | "01010000000", -- add |
| 86 | + | "00000000"); |
| 87 | - | "00100001110", -- pushr botR |
| 87 | + | |
| 88 | - | "10000000000", -- sub |
| 88 | + | |
| 89 | - | "10010000000", -- abs |
| 89 | + | Write: process(Data_Read, Data_Adr, Data_In) |
| 90 | - | "00100001100", -- pushr botL |
| 90 | + | |
| 91 | - | "00100001101", -- pushr bot |
| 91 | + | if (Data_Read = '0') then |
| 92 | - | "00010000010", -- pushc 2 |
| 92 | + | Ram(CONV_INTEGER(Data_Adr)) <= Data_In; |
| 93 | - | "01110000000", -- mul |
| 93 | + | |
| 94 | - | "01010000000", -- add |
| 94 | + | end process; |
| 95 | - | "00100001110", -- pushr botR |
| 95 | + | |
| 96 | - | "01010000000", -- add |
| 96 | + | Read: process(Data_Read, Data_Adr) |
| 97 | - | "00100000111", -- pushr topL |
| 97 | + | |
| 98 | - | "10000000000", -- sub |
| 98 | + | if (Data_Read = '1') then |
| 99 | - | "00100001000", -- pushr top |
| 99 | + | Data_Out <= Ram(CONV_INTEGER(Data_Adr)); |
| 100 | - | "00010000010", -- pushc 2 |
| 100 | + | else |
| 101 | - | "01110000000", -- mul |
| 101 | + | Data_Out <= (others => 'Z'); |
| 102 | - | "10000000000", -- sub |
| 102 | + | |
| 103 | - | "00100001001", -- pushr topR |
| 103 | + | |
| 104 | - | "10000000000", -- sub |
| 104 | + | |
| 105 | - | "10010000000", -- abs |
| 105 | + | end DataRAM_arch; |