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| 1 | ------------------------------------------------ | |
| 2 | CPU: 0, Freeze: 256549922 cycles, Trace Points: 100 (+10) | |
| 3 | Calibrated minimum trace-point overhead: 0.000 us | |
| 4 | ||
| 5 | +----- Hard IRQs ('|': locked)
| |
| 6 | |+-- Xenomai | |
| 7 | ||+- Linux ('*': domain stalled, '+': current, '#': current+stalled)
| |
| 8 | ||| +---------- Delay flag ('+': > 1 us, '!': > 10 us)
| |
| 9 | ||| | +- NMI noise ('N')
| |
| 10 | ||| | | | |
| 11 | Type User Val. Time Delay Function (Parent) | |
| 12 | : #func -38 0.000 dwc_otg_is_host_mode+0x10 (dwc_otg_hcd_handle_intr+0x5c) | |
| 13 | : #func -38 0.500 DWC_READ_REG32+0x10 (dwc_otg_is_host_mode+0x20) | |
| 14 | : #func -37 0.500 DWC_READ_REG32+0x10 #func -37 0.500 dwc_otg_hcd_handle_hc_intr+0x10 (dwc_otg_hcd_handle) | |
| 15 | -36 0.500 DWC_READ_REG32+0x10 (dwc_otg_hcd_handle_hc_intr+0x2c) | |
| 16 | : #func -36 0.000 DWC_SPINUNLOCK+0x10 (dwc_otg_hcd_handle_intr+0xcc) | |
| 17 | : #func -36 PINUNLOCK+0x18) | |
| 18 | : #func -35 0.500 add_interrupt_randomness+0x14 (handle_irq_event_percpu+0x140) | |
| 19 | : #func -35 0.500 read_current_timer+0x10 (add_interrupt_randomness+0x38) | |
| 20 | : #func -34 0.500 bcm2708_read_current_timer+0x10 (read_current_timer+0x30) | |
| 21 | : #func -34 0.500 note_interrupt+0x14 (handle_irq_event_percpu+0x160) | |
| 22 | : #func -33 0.500 ipipe_root_only+0x10 (handle_irq_event+0x80) | |
| 23 | : #func -33 0.000 unmask_irq+0x10 (handle_level_irq+0xe8) | |
| 24 | :| #begin 0x80000001 -33 0.500 unmask_irq+0x60 (handle_level_irq+0xe8) | |
| 25 | :| #func -32 0. -32 0.000 irq_trl_unmask_irq+0x50) | |
| 26 | :| #end 0x80000001 -32 0.500 unmask_irq+0x84 (handle_level_irq+0xe8) | |
| 27 | :| #begin 0x90000000 -31 0.500 __irq_svc+0x44 (unmask_irq+0x54) | |
| 28 | :| #func -31 rq_svc+0x4c) | |
| 29 | :| #beg004b -30 0.500 __ipipe_grab_irq+0x24 (__irq_svc+0x4c) | |
| 30 | :| #func -30 0.500 __ipipe_dispatch_irq+0x10 (__ipipe_grab_irq+0x48) | |
| 31 | :| #func -29 0.500 __ipipe_ack_irq+0x10 (__ipipe_dispatch_irq+0x1fc) | |
| 32 | :| #func irq+0x10 (__ipipe_ack_irq+0x1c) | |
| 33 | :|00 armctrl_nc ta+0x10 (armding+0x10 (_ -27+0x10 (__ipi 0x000000pe_grab_irq 0x10 (__ipipe_grab_irq+__ipipe_che #func ) | |
| 34 | : #funnc -24 0.500 idle_cpu+0x10 (irq_exit+0x5c) | |
| 35 | : #func -23 0.500 rcu_irq_exit+0x10 (irq_exit+0x90) | |
| 36 | :| #begin 0x80000001 -23 0.500 rcu_irq_exit+0x80 (irq_exit+0x90) | |
| 37 | :| #end 0x80000001 -22 0.000 rcu_irq_exit+0x98 (irq_exit+0x90) | |
| 38 | : #func -22 0.500 ipipe_root_only+0x10 (irq_exit+0x98) | |
| 39 | :| #begin 0x80000000 -22 1.000 __ipipe_do_sync_stage+0x1fc (ipipe_unstall_root+0x70) | |
| 40 | :| #end 0x80000000 -21 0.500 __ipipe_do_sync_stage+0x208 (ipipe_unstall_root+0x70) | |
| 41 | : #func -20 0.000 __ipipe_do_IRQ+0x10 (__ipipe_do_sync_stage+0x1e4) | |
| 42 | : #func -20 0.500 handle_IRQ+0x10 (__ipipe_do_IRQ+0x1c) | |
| 43 | : #func -20 0.500 irq_enter+0x10 (handle_IRQ+0x2 0.000 rcu_irq_enter+0x10 (irq_enter+0x24) | |
| 44 | :| #begin 0x80000001 -19 0.500 rcu_irq_enter+0xa8 (irq_enter+0x24) | |
| 45 | :| #end 0x80000001 -19 0.500 rcu_irq_enter+0xc0 (irq_enter+0x24) | |
| 46 | : #func -18 0.000 ipipe_root_only+0x10 (irq_enter+0x50) | |
| 47 | : #func -18 0.500 generic_handle_irq+0x10 (handle_IRQ+0x40) | |
| 48 | : #func -18 0.500 handle_level_irq+0x10 (generic_handle_irq+0x2c) | |
| 49 | : #func -17 0.500 ipipe_root_only+0x10 (handle_level_irq+0x24) | |
| 50 | : #func -17 0.000 handle_irq_event+0x10 (handle_level_irq+0x8c) | |
| 51 | : #func -17 0.500 ipipex38) | |
| 52 | : -16 0.500 handle_irq_event_percpu+0x14 (handle_irq_event+0x74) | |
| 53 | : #func -16 0.500 dwc_otg_common_irq+0x10 (handle_irq_event_percpu+0x60) | |
| 54 | : #func -15 0.000 dwc_otg_handle_common_intr+0x14 (dwc_otg_common_irq+0x1c) | |
| 55 | : #func -15 0.500 DWC_READ_REG32+0x10 (dwc_otg_handle_common_intr+0x2c) | |
| 56 | : #func -15 0.500 dwc_otg_is_device_mode+0x10 (dwc_otg_handle_common_intr+0x38) | |
| 57 | : #func -14 0.500 DWC_READ_REG32+0x10 (dwc_otg_is_device_mode+0x20) | |
| 58 | : #func -14 0.000 DWC_SPINLOCK+0x10 (dwc_otg_handle #func -14 0.500 ipipe_root_only+0x10 (DWC_SPINLOCK+0x18) | |
| 59 | : #func -13 0.000 dwc_otg_is_device_mode+0x10 (dwc_otg_handle_common_intr+0x30c) | |
| 60 | : #func -13 0.500 DWC_READ_REG32+0x10 (dwc_otg_is_device_mode+0x20) | |
| 61 | : #func -13 0.500 DWC_READ_dle_common_intr+0x328) | |
| 62 | : #func -12 0.500 DWC_READ_REG32+0x10 (dwc_otg_handle_common_intr+0x338) | |
| 63 | :| #begin 0x80000001 -12 0.500 dwc_otg_handle_common_intr+0xbe8 (dwc_otg_common_irq+0x1c) | |
| 64 | :| #end 0x80000001 -11 0.500 dwc_otg_handle_common_intr+0xc04 (dwc_otg_common_irq+0x1c) | |
| 65 | : -11 0.000 DWC_READ_REG32+0x10 (dwc_otg_handle_common_intr+0x394) | |
| 66 | : #func -11 0.500 DWC_WRITE_REG32+0x10 (dwc_otg_handle_common_intr+0x57c) | |
| 67 | : #func -10 0.500 DWC_SPINUNLOCK+0x10 (dwc_otg_handle_common_intr+0xcc) | |
| 68 | : #func -10 0.500 ipipe_root_only+0x10 ( #func -9 0.000 dwc_otg_pcd_irq+0x10 (handle_irq_event_percpu+0x60) | |
| 69 | : #func -9 0.500 dwc_otg_pcd_handle_intr+0x10 (dwc_otg_pcd_irq+0x1c) | |
| 70 | : #func -9 0.000 dwc_otg_is_device_mode+0x10 (dwc_otg_pcd_handle_intr+0x30) | |
| 71 | : #func dwc_otg_is_device_mode+0x20) | |
| 72 | : -8 0.500 usb_hcd_irq+0x14 (handle_irq_event_percpu+0x60) | |
| 73 | :| #begin 0x80000001 -8 0.500 usb_hcd_irq+0x94 (handle_irq_event_percpu+0x60) | |
| 74 | :| #end 0x80000001 -7 0.500 usb_hcd_irq+0xac (handle_irq_event_percpu+0x60) | |
| 75 | : #func -7 0.000 dwc_otg_hcd_irq+0x10 (usb_hcd_irq+0x68) | |
| 76 | : #func -7 0.500 dwc_otg_hcd_handle_intr+0x10 (dwc_otg_hcd_irq+0x1c) | |
| 77 | : #func -6 0.000 DWC_READ_REG32+0x10 (dwc_otg_hcd_handle_intr+0x28) | |
| 78 | : #func -6 0.500 DWC_READ_REG32+0x10 (dwc_otg_hcd_handle_intr+0x38) | |
| 79 | : #func OCK+0x10 (dwc_otg_hcd_handle_intr+0x54) | |
| 80 | : #func -5 0.000 ipipe_root_only+0x10 (DWC_SPINLOCK+0x18) | |
| 81 | : #func -5 0.500 dwc_otg_is_host_mode+0x10 (dwc_otg_hcd_handle_intr+0x5c) | |
| 82 | : #func -5 0.500 DWC_READ_REG32+0x10 (dwc_otg_is_host_mode+0x20) | |
| 83 | :00 DWC_READ_REG32+0x10 (dwc_otg_hcd_handle_intr+0x11c) | |
| 84 | : #func -4 0.000 dwc_otg_hcd_handle_hc_intr+0x10 (dwc_otg_hcd_handle_intr+0x1d8) | |
| 85 | : #func -4 1.000 DWC_READ_REG32+0x10 (dwc_otg_hcd_handle_hc_intr+0x2c) | |
| 86 | : #func -3 0.000 DWC_SPINUNLOCK+0x10 (dwc_oc -3 0.500 ipipe_root_only+0x10 (DWC_SPINUNLOCK+0x18) | |
| 87 | : #func -2 0.500 add_interrupt_randomness+0x14 (handle_irq_event_percpu+0x140) | |
| 88 | : #func -2 0.500 read_current_timer+0x10 (add_interrupt_randomness+0x38) | |
| 89 | : #func -1 0.5t_timer+0x10 (read_current_timer+0x30) | |
| 90 | : #func -1 0.500 note_interrupt+0x14 (handle_irq_event_percpu+0x160) | |
| 91 | : #func 0 0.500 __report_bad_irq.isra.6+0x10 (note_interrupt+0x17c) | |
| 92 | < #freeze 0x00000000 0 1.000 ipipe_trace_freeze+0x20 (__report_bad_irq.isra.6+0x28) | |
| 93 | 1 0.500 printk+0x18 (__report_bad_irq.isra.6+0x3c) | |
| 94 | | #begin 0x80000001 1 1.000 printk+0x3c (__report_bad_irq.isra.6+0x3c) | |
| 95 | | #end 0x80000001 2 0.500 printk+0xec (__report_bad_irq.isra.6+0x3c) | |
| 96 | #func 3 1.000 vprintk_emit+0x14 (printk+0x118) | |
| 97 | | #begin 0x80000024 (printk+0x118) | |
| 98 | | #end 0x80000001 4 0.500 vprintk_emit+0x33c (printk+0x118) | |
| 99 | #func 5 11.000 ipipe_root_only+0x10 (vprintk_emit+0x14c) | |
| 100 | #func 16 4.500 log_store+0x14 (vprintk_emit+0x234) | |
| 101 | #func 20 0.500 console_trylock+0x | |
| 102 | #func_trylock+0x10 (console_trylock+0x1c) |
