View difference between Paste ID: FPw6unFZ and UHycWQqX

 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.STD_LOGIC_ARITH.ALL;
 use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 entity MUX_2_1 is
-Port ( a,b,S : in std_logic;
+Port (
 a,b,S : in std_logic;
 O : out std_logic;
 )
 end MUX_2_1;
-P1: process (a, b, S)
+
-   begin
+
 begin
 if (S = '0' ) then
           O <= a;
 else
 	O <= b;
 end if;
-   end process P1;
+