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| 1 | jay@aura-R528 syn$ make distclean | |
| 2 | rm -rf *.ngc *.ncd *.ngd *.bit | |
| 3 | make clean | |
| 4 | make[1]: Entering directory `/home/aurabindo/minsoc/syn' | |
| 5 | rm -rf _xmsgs xst xlnx_auto_0_xdb | |
| 6 | rm -rf *.xst *.xrpt *.srp *.lso *.log *.bld *.lst *.twr *.ise *.map *.mrp *.ngm *.pcf *.psr *.xml *.pad *.par *.ptwx *.bgn *.unroutes *.xpi minsoc_par_pad* *.xwbt *.html | |
| 7 | make[1]: Leaving directory `/home/aurabindo/minsoc/syn' | |
| 8 | jay@aura-R528 syn$ make or1200 | |
| 9 | make prepare | |
| 10 | make[1]: Entering directory `/home/aurabindo/minsoc/syn' | |
| 11 | rm -rf xst | |
| 12 | mkdir xst | |
| 13 | make[1]: Leaving directory `/home/aurabindo/minsoc/syn' | |
| 14 | xst -ifn "..//syn/buildSupport/or1200_top.xst" | |
| 15 | Release 13.2 - xst O.61xd (lin) | |
| 16 | Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. | |
| 17 | --> | |
| 18 | Parameter TMPDIR set to ./xst | |
| 19 | ||
| 20 | ||
| 21 | Total REAL time to Xst completion: 2.00 secs | |
| 22 | Total CPU time to Xst completion: 0.14 secs | |
| 23 | ||
| 24 | --> | |
| 25 | ||
| 26 | TABLE OF CONTENTS | |
| 27 | 1) Synthesis Options Summary | |
| 28 | 2) HDL Compilation | |
| 29 | 3) Design Hierarchy Analysis | |
| 30 | 4) HDL Analysis | |
| 31 | 5) HDL Synthesis | |
| 32 | 5.1) HDL Synthesis Report | |
| 33 | 6) Advanced HDL Synthesis | |
| 34 | 6.1) Advanced HDL Synthesis Report | |
| 35 | 7) Low Level Synthesis | |
| 36 | 8) Partition Report | |
| 37 | 9) Final Report | |
| 38 | 9.1) Device utilization summary | |
| 39 | 9.2) Partition Resource Summary | |
| 40 | 9.3) TIMING REPORT | |
| 41 | ||
| 42 | ||
| 43 | ========================================================================= | |
| 44 | * Synthesis Options Summary * | |
| 45 | ========================================================================= | |
| 46 | ---- Source Parameters | |
| 47 | Verilog Include Directory : { "/home/aurabindo/minsoc/prj/../rtl/verilog/or1200/rtl/verilog" }
| |
| 48 | Input File Name : "/home/aurabindo/minsoc/prj/../prj/xilinx/or1200_top.prj" | |
| 49 | Input Format : Verilog | |
| 50 | ||
| 51 | ---- Target Parameters | |
| 52 | Output File Name : "or1200_top" | |
| 53 | Output Format : NGC | |
| 54 | Target Device : xc3s500e-4-fg320 | |
| 55 | ||
| 56 | ---- Source Options | |
| 57 | Top Module Name : or1200_top | |
| 58 | ||
| 59 | ---- Target Options | |
| 60 | Add IO Buffers : no | |
| 61 | ||
| 62 | ---- General Options | |
| 63 | Optimization Goal : Speed | |
| 64 | Optimization Effort : 1 | |
| 65 | ||
| 66 | ========================================================================= | |
| 67 | ||
| 68 | ||
| 69 | ========================================================================= | |
| 70 | * HDL Compilation * | |
| 71 | ========================================================================= | |
| 72 | Compiling verilog file "/home/aurabindo/minsoc/prj/../prj/xilinx/or1200_top.prj" in library work | |
| 73 | ERROR:HDLParsers:3464 - Library work mapped to physical location xst/work does not exist. | |
| 74 | ERROR:HDLCompilers:219 - Open of logical library 'work' failed | |
| 75 | Analysis of file <"/home/aurabindo/minsoc/prj/../prj/xilinx/or1200_top.prj"> failed. | |
| 76 | --> | |
| 77 | ||
| 78 | ||
| 79 | Total memory usage is 147460 kilobytes | |
| 80 | ||
| 81 | Number of errors : 2 ( 0 filtered) | |
| 82 | Number of warnings : 0 ( 0 filtered) | |
| 83 | Number of infos : 0 ( 0 filtered) | |
| 84 | ||
| 85 | make: *** [or1200_top.ngc] Error 6 |
