View difference between Paste ID: 0JVhwd8u and Aq79J9bR

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 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 
 
 entity nasobicka is
     Port ( s : in  STD_LOGIC;
            x : in  STD_LOGIC_VECTOR (width-1 downto 0);
            y : in  STD_LOGIC_VECTOR (width-1 downto 0);
            P : in  STD_LOGIC_VECTOR (2*width-1 downto 0);
            done : out  STD_LOGIC);
 end nasobicka;
 
 architecture Behavioral of nasobicka is
 
 signal NL,NC : unsigned (width-1 downto 0);
 signal SC: unsigned (width downto 0);
 signal PC: integer range 0 to width;
 
 type states is (smart, init, add, shift_NL,shift_SC,stop);
 signal state, next_state : state := start;
 
 signal l1,l3 : std_logic;
 signal r_start : std_logic;
 signal R : std_logic_vector(1 to 6);
 
 begin
 	l1 <= '1' when NL(0) = '1' else '0';
 	l3 <= '1' when PC < width else'0';
 
 	NL_reg: process(clk) is
 		begin
 			if rising_edge(clk) then
 				if r_start = '1' then
 					NL <= x;
 				elsif R (4) = '1' then
 					NL <= SC(0) & NL(width-1 downto 1);
 					end if;
 					end if;
 					end process;
 
 					NC_reg: process (clk) is
 						begin
 							if rising_edge(clk) then
 								if r_start = '1' then
 									NC <= y;
 								end if;
 							end if;
 						end process;
 
 					SC_reg: process (clk) is
 						begin
 							if rising_edge(clk) then
 								if R (1) = '1' then
 									SC <= (others => '0');
 									elsif R(3) = '1' then
-									SC <= resize (SC+NC,Sc'length);
+									SC <= resize (SC+NC,SC'length);
 									elsif R(5) = '1' then
 									SC <= '0' & SC(width downto 1);
 								end if;
 							end if;
 						end process;
 
 			P <= SC(width -1 downto 0) & NL;
 
 			PC_reg: process (clk) is
 				begin
 					if rising_edge(clk) then
 						if R(2) = '1' then
 							PC<=0;
 						elsif R(6) = '1' then
 							PC <=PC+1;
 						end if;
 					end if;
 				end process;
 
 				process (clk)
 					begin
 						if rising_edge(clk)
 							then state <= next_state;
 						end if;
 					end process;
 
 				process (state,s,l1,l3)
 					begin
 						next_state <= state;
 
 						case state is
 							when start =>
 								if (s = '1') then
 									next_state <= init;
 								else
 									next_state <= start;
 								end if;
 							when init =>
 									if(l1 = '1') then
 										next_state <= add;
 									else
 										next_state <=shift_NL;
 									end if;
 							when add =>
 								next_state <= shift_NL;
 							when shift_NL =>
 								next_state <= shift_SC;
 							when shift_SC =>
 								if (l3 = '1' and l1 = '1') then
 									next_state <= add;
 								elsif (l3 = '1' and l1 = '0') then
 									next_state <= shift_NL;
 								else
 								next_state <=  stop;
 							end if;
 						when stop =>
 								next_state <= start;
 							when others => null;
 					end case;
 end process;
 
 process (state)
 	begin
 		done <= '0';
 		r_start <= '0';
 		R<= (others => '0');
 
 
 		case state is
 				when start =>
 					r_start <= '1';
 					done <= '0';
 				when init =>
 					R(1 to 2) <= "l1";
 				when add =>
 					R(3) <= '1';
 				when shift_NL =>
 				R(4) <= '1';
 				R (6) <= '1';
 
 				when shift_SC =>
 				R(5) <= '1';
 
 				when stop =>
 				done <= '1';
 				when others => null;
 			end case;
 			end process;
 
 end Behavioral;