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lucmann

drm_sched_init

Feb 27th, 2025
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  1. ret = drm_sched_init(&js->queue[j].sched,
  2. &panfrost_sched_ops, NULL,
  3. DRM_SCHED_PRIORITY_COUNT,
  4. nentries, 0,
  5. msecs_to_jiffies(JOB_TIMEOUT_MS),
  6. pfdev->reset.wq,
  7. NULL, "pan_js", pfdev->dev);
  8. ret = drm_sched_init(&v3d->queue[V3D_BIN].sched,
  9. &v3d_bin_sched_ops, NULL,
  10. DRM_SCHED_PRIORITY_COUNT,
  11. hw_jobs_limit, job_hang_limit,
  12. msecs_to_jiffies(hang_limit_ms), NULL,
  13. NULL, "v3d_bin", v3d->drm.dev);
  14. ret = drm_sched_init(&v3d->queue[V3D_RENDER].sched,
  15. &v3d_render_sched_ops, NULL,
  16. DRM_SCHED_PRIORITY_COUNT,
  17. hw_jobs_limit, job_hang_limit,
  18. msecs_to_jiffies(hang_limit_ms), NULL,
  19. NULL, "v3d_render", v3d->drm.dev);
  20. ret = drm_sched_init(&v3d->queue[V3D_TFU].sched,
  21. &v3d_tfu_sched_ops, NULL,
  22. DRM_SCHED_PRIORITY_COUNT,
  23. hw_jobs_limit, job_hang_limit,
  24. msecs_to_jiffies(hang_limit_ms), NULL,
  25. NULL, "v3d_tfu", v3d->drm.dev);
  26. ret = drm_sched_init(&v3d->queue[V3D_CSD].sched,
  27. &v3d_csd_sched_ops, NULL,
  28. DRM_SCHED_PRIORITY_COUNT,
  29. hw_jobs_limit, job_hang_limit,
  30. msecs_to_jiffies(hang_limit_ms), NULL,
  31. NULL, "v3d_csd", v3d->drm.dev);
  32. ret = drm_sched_init(&v3d->queue[V3D_CACHE_CLEAN].sched,
  33. &v3d_cache_clean_sched_ops, NULL,
  34. DRM_SCHED_PRIORITY_COUNT,
  35. hw_jobs_limit, job_hang_limit,
  36. msecs_to_jiffies(hang_limit_ms), NULL,
  37. NULL, "v3d_cache_clean", v3d->drm.dev);
  38. ret = drm_sched_init(&v3d->queue[V3D_CPU].sched,
  39. &v3d_cpu_sched_ops, NULL,
  40. DRM_SCHED_PRIORITY_COUNT,
  41. 1, job_hang_limit,
  42. msecs_to_jiffies(hang_limit_ms), NULL,
  43. NULL, "v3d_cpu", v3d->drm.dev);
  44. err = drm_sched_init(&exl->sched, &drm_sched_ops, NULL, 1,
  45. q->lrc[0]->ring.size / MAX_JOB_SIZE_BYTES,
  46. XE_SCHED_HANG_LIMIT, XE_SCHED_JOB_TIMEOUT,
  47. NULL, NULL, q->hwe->name,
  48. gt_to_xe(q->gt)->drm.dev);
  49. ret = drm_sched_init(&gpu->sched, &etnaviv_sched_ops, NULL,
  50. DRM_SCHED_PRIORITY_COUNT,
  51. etnaviv_hw_jobs_limit, etnaviv_job_hang_limit,
  52. msecs_to_jiffies(500), NULL, NULL,
  53. dev_name(gpu->dev), gpu->dev);
  54. ret = drm_sched_init(drm_sched, &nouveau_sched_ops, wq,
  55. NOUVEAU_SCHED_PRIORITY_COUNT,
  56. credit_limit, 0, timeout,
  57. NULL, NULL, "nouveau_sched", drm->dev->dev);
  58. ret = drm_sched_init(&vm->sched, &panthor_vm_bind_ops, ptdev->mmu->vm.wq,
  59. 1, 1, 0,
  60. MAX_SCHEDULE_TIMEOUT, NULL, NULL,
  61. "panthor-vm-bind", ptdev->base.dev);
  62. ret = drm_sched_init(&queue->scheduler, &panthor_queue_sched_ops,
  63. group->ptdev->scheduler->wq, 1,
  64. args->ringbuf_size / sizeof(u64),
  65. 0, msecs_to_jiffies(JOB_TIMEOUT_MS),
  66. group->ptdev->reset.wq,
  67. NULL, "panthor-queue", group->ptdev->base.dev);
  68. err = drm_sched_init(&queue->scheduler,
  69. &pvr_queue_sched_ops,
  70. pvr_dev->sched_wq, 1, 64 * 1024, 1,
  71. msecs_to_jiffies(500),
  72. pvr_dev->sched_wq, NULL, "pvr-queue",
  73. pvr_dev->base.dev);
  74. r = drm_sched_init(&ring->sched, &amdgpu_sched_ops, NULL,
  75. DRM_SCHED_PRIORITY_COUNT,
  76. ring->num_hw_submission, 0,
  77. timeout, adev->reset_domain->wq,
  78. ring->sched_score, ring->name,
  79. adev->dev);
  80. ret = drm_sched_init(&ring->sched, &msm_sched_ops, NULL,
  81. DRM_SCHED_PRIORITY_COUNT,
  82. num_hw_submissions, 0, sched_timeout,
  83. NULL, NULL, to_msm_bo(ring->bo)->name, gpu->dev->dev);
  84.  
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