3

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity TestGen is
generic(N: integer range 0 to 32 := 8);
port (
clk    : out std_logic;
reset  : out std_logic;
div  : out UNSIGNED(N-1 downto 0));
end TestGen;


architecture Stim of TestGen is
begin
	reset <= '1' after 0 ps,
			     '0' after 10 ps, '1' after 600 ps,
	         '0' after 2.4 ns, '1' after 3 ns,
	         '0' after 6 ns, '1' after 6.6 ns,
	         '0' after 11.4 ns, '1' after 12 ns,
	         '0' after 17.4 ns, '1' after 18 ns;


	div <= "00000000",
	       "00000001" after 2.4 ns,
	       "00000010" after 6 ns,
	       "00000011" after 11.4 ns,
	       "00000100" after 17.4 ns;


	Clock: process
	begin
		clk <= '0';
		wait for 300 ps;
		clk <= '1';
		wait for 300 ps;
	end process Clock;


	stopsim: process
	begin
	  wait for 25 ns;
	  assert false
	  report "koniec"
	  severity failure;
	end process stopsim;
end Stim;