mac_reduced.v

module mac(in1, in2, clk, reset, acc);
   input signed [3:0] in1;
   input signed [3:0] in2;
   input       clk;
   output reg signed [4:0] acc;
   input        reset;

   reg signed [7:0]   out_mult;
   reg signed [9:0]   acc_pre_reduced;

   always @(posedge clk or posedge reset)
     begin
        out_mult <= in1*in2;
        if (reset)
          acc_pre_reduced <= 0;
        else
          acc_pre_reduced = out_mult+acc_pre_reduced;
          if (acc_pre_reduced > 2**3)        acc = 2**3-1;
          else if (acc_pre_reduced < -2**3)  acc = -2**3;
          else acc = acc_pre_reduced;

     end

endmodule