`timescale 1ns/1ps
module counter_test;
integer i;
logic clk, resetn;
logic [3:0] result;
logic [1:0] mode;
initial begin
clk=0;
forever #10 clk = ~clk;
end
initial
begin
resetn=0;
mode = 2'b00;
#10 resetn=1;
for(int i=0; i<45; i=i+1) #20 $strobe("Counter value: %d", result);
mode = 2'b01;
for(int i=0; i<45; i=i+1) #20 $strobe("Counter value: %d", result);
mode = 2'b11;
for(int i=0; i<45; i=i+1) #20 $strobe("Counter value: %d", result);
mode = 2'b10;
for(int i=0; i<45; i=i+1) #20 $strobe("Counter value: %d", result);
#100 resetn=0;
#10 resetn=1;
#100 $stop;
end
bin_cnt uut_inst(clk, resetn, mode, result);
endmodule