Shift Add Multiplier

//============================
// Top Module
//============================

`timescale 1ns / 1ps

//Shift-Add Mplier
//Checks Mplier bit [0] => If 1 => Add Mcand to Accumulator,
//                         If 0 => Skip
//Right Shift Mplier, Left Shift Mcand
//Repeat Until all Mplier Bits have been checked.

module ShiftAdd_Mplier #(parameter WIDTH = 2)
    (
    input logic clk, srst, Mul_Start,
    input logic [WIDTH - 1 : 0] Mplier, Mcand,
    output logic [2*WIDTH - 1 : 0] Product,
    output logic Done
    );
    logic Acc_en, R_Shift, L_Shift, R_Shift_Done, L_Shift_Done, Acc_Done;

    logic [$clog2(WIDTH + 1) - 1:0] Mplier_Bit_Count;
    logic [2*WIDTH - 1 : 0] temp_Mcand; logic [WIDTH - 1 : 0] temp_Mplier;
    logic [2*WIDTH - 1: 0] Acc_Out, temp_Sum;
    logic [WIDTH - 1 : 0] temp_reg1;
    logic [2*WIDTH - 1: 0] temp_reg2;

    Shifter #(.WIDTH(WIDTH)) R_Shifter(
                                           .clk(clk),
                                           .srst(srst),
                                           .R_Shift(R_Shift),
                                           .L_Shift(0),
                                           .In(temp_Mplier),
                                           .Shifter_Out(temp_reg1),
                                           .Shift_Done(R_Shift_Done)
                                           );

    Shifter #(.WIDTH(2*WIDTH)) L_Shifter(
                                           .clk(clk),
                                           .srst(srst),
                                           .R_Shift(0),
                                           .L_Shift(L_Shift),
                                           .In(temp_Mcand),
                                           .Shifter_Out(temp_reg2),
                                           .Shift_Done(L_Shift_Done)
                                           );

    Carry_LookAhead #(.WIDTH(2*WIDTH)) CLA(    .clk(clk),
                                               .srst(srst),
                                               .A(temp_Mcand),
                                               .B(Acc_Out),
                                               .Cin(0),
                                               .Sum(temp_Sum)
                                               );

    Accumulator #(.WIDTH(2*WIDTH)) Acc(
                                         .clk(clk),
                                         .srst(srst),
                                         .Acc_en(Acc_en),
                                         .Acc_In(temp_Sum),
                                         .Acc_Out(Acc_Out),
                                         .Acc_Done(Acc_Done)
                                         );


    always_ff @(posedge clk) begin
        if (srst) begin
            temp_Mcand      <= 0;
            temp_Mplier     <= 0;
            Product         <= 0;
            Mplier_Bit_Count<= 0;
            Done            <= 0;
            L_Shift         <= 0;
            R_Shift         <= 0;
            Acc_en          <= 0;
        end
        else if (!L_Shift && !R_Shift && !Acc_en) begin //if not performing Shifting or accumulating Operations
            if (Mul_Start) begin
                temp_Mcand             <= {{WIDTH{1'b0}}, Mcand};
                temp_Mplier            <= Mplier;
                Mplier_Bit_Count       <= WIDTH;
            end
            else if (Mplier_Bit_Count != 0) begin
                L_Shift            <= 1;
                R_Shift            <= 1;
                Mplier_Bit_Count   <= Mplier_Bit_Count - 1;
                if (temp_Mplier[0]) begin
                    Acc_en <= 1;
                end
                if (Mplier_Bit_Count == WIDTH - 1) begin
                    Done <= 1;
                end
            end
            if (Done) begin
                Product <= Acc_Out[2*WIDTH - 1 : 0];
            end
        end
        else begin
            if (L_Shift) begin
                if (L_Shift_Done) begin
                    L_Shift    <= 0;
                    temp_Mcand <= temp_reg2;
                end
            end
            if (R_Shift) begin
                if (R_Shift_Done) begin
                    R_Shift     <= 0;
                    temp_Mplier <= temp_reg1;
                end
            end
            if (Acc_en) begin
                if (Acc_Done) begin
                    Acc_en <= 0;
                end
            end
        end
    end
endmodule

//============================
// Shifter Module
//============================

`timescale 1ns / 1ps
module Shifter #(parameter WIDTH = 4)
    (
    input logic clk, srst, R_Shift, L_Shift,
    input logic [WIDTH - 1 : 0] In,
    output logic [WIDTH - 1 : 0] Shifter_Out,
    output logic Shift_Done
    );

    always_ff @(posedge clk) begin
        if (srst) begin
            Shifter_Out <= 0;
            Shift_Done <= 0;
        end
        else if (R_Shift) begin
            Shifter_Out <= In >> 1;
            Shift_Done <= 1;
        end
        else if (L_Shift) begin
            Shifter_Out <= In << 1;
            Shift_Done <= 1;
        end
        else if (!L_Shift || !R_Shift) begin
            Shift_Done <= 0;
        end
    end
endmodule

//============================
// Carry Lookahead Adder Module
//============================

`timescale 1ns / 1ps
module Carry_LookAhead #(parameter WIDTH = 4)
    (
    input logic [WIDTH - 1:0] A, B,
    input logic Cin, clk, srst,
    output logic [WIDTH - 1:0] Sum,
    output logic Cout
    );
    logic [WIDTH - 1:0] Gen, Prop, temp_Sum; logic [WIDTH:0] Carry_in;

    assign Carry_in[0] = Cin;
    genvar i;
    generate
        for( i = 0; i < WIDTH; i++) begin : LookAhead
            Full_Adder Full_Adder_inst
                (
                    .A(A[i]),
                    .B(B[i]),
                    .Cin(Carry_in[i]),
                    .Sum(temp_Sum[i]),
                    .Cout()
                    );
        end
    endgenerate

    genvar j;
    generate
        for( j = 0; j < WIDTH; j++) begin
            assign Gen[j] = A[j] & B[j];
            assign Prop[j] = A[j] | B[j];
            assign Carry_in[j+1] = Gen[j] | (Prop[j] & Carry_in[j]);
        end
    endgenerate
    always_ff @(posedge clk) begin
        if (srst) begin
            Sum <= 0;
            Cout <= 0;
        end
        else begin
            Sum <= temp_Sum;
            Cout <= Carry_in[WIDTH];
        end
    end
endmodule

`timescale 1ns / 1ps
//==================================================
//FULL ADDER Implementation
//==================================================
module Full_Adder(
    input logic A,
    input logic B,
    input logic Cin,
    output logic Sum,
    output logic Cout
    );

    assign Sum = A ^ B ^ Cin;
    assign Cout = A&B | A&Cin | B&Cin;
endmodule


//============================
// Accumulator Module
//============================

`timescale 1ns / 1ps
module Accumulator #(parameter WIDTH = 4)
    (
    input logic clk, srst, Acc_en,
    input logic [WIDTH - 1 : 0] Acc_In,
    output logic [WIDTH - 1: 0] Acc_Out,
    output logic Acc_Done
    );

    always_ff @(posedge clk) begin
        if (srst) begin
            Acc_Out <= 0;
        end
        else if (Acc_en) begin
            Acc_Out <= Acc_In;
            Acc_Done <= 1;
        end
        else if (!Acc_en) begin
            Acc_Done <= 0;
        end
    end

endmodule