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- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- entity Bola8 is
- Port ( A, B: in std_logic_vector(7 downto 0);
- Cin: in std_logic;
- Cout: out std_logic;
- Bnegado: in std_logic;
- Puntos: out std_logic_vector(7 downto 0));
- signal ALUS0, ALUS1, ALUS2, ALUS3, ALUS4, ALUS5, ALUS6, ALUS7: std_logic;
- signal Co0, Co1, Co2, Co3, Co4, Co5, Co6, Co7: std_logic;
- end Bola8;
- architecture Behavioral of Bola8 is
- component ALUS
- Port ( A,B: in std_logic;
- Cin: in std_logic;
- Cout: out std_logic;
- Bnegado: in std_logic;
- Puntaje: out std_logic);
- end component;
- begin
- Puntos <= ALUS7 & ALUS6 & ALUS5 & ALUS4 & ALUS3 & ALUS2 & ALUS1 & ALUS0;
- A0: ALUS port map ( A=> A(0), B=> B(0),
- Cin=>Cin, Cout=>Co0,
- Bnegado=> Bnegado,
- Puntaje=>ALUS0);
- A1: ALUS port map ( A=> A(1), B=> B(1),
- Cin=>Co0, Cout=>Co1,
- Bnegado=> Bnegado,
- Puntaje=>ALUS1);
- A2: ALUS port map ( A=> A(2), B=> B(2),
- Cin=>Co1, Cout=>Co2,
- Bnegado=> Bnegado,
- Puntaje=>ALUS2);
- A3: ALUS port map ( A=> A(3), B=> B(3),
- Cin=>Co2, Cout=>Co3,
- Bnegado=> Bnegado,
- Puntaje=>ALUS3);
- A4: ALUS port map ( A=> A(4), B=> B(4),
- Cin=>Co3, Cout=>Co4,
- Bnegado=> Bnegado,
- Puntaje=>ALUS4);
- A5: ALUS port map ( A=> A(5), B=> B(5),
- Cin=>Co4, Cout=>Co5,
- Bnegado=> Bnegado,
- Puntaje=>ALUS5);
- A6: ALUS port map ( A=> A(6), B=> B(6),
- Cin=>Co5, Cout=>Co6,
- Bnegado=> Bnegado,
- Puntaje=>ALUS6);
- A7: ALUS port map ( A=> A(7), B=> B(7),
- Cin=>Co6, Cout=>Cout,
- Bnegado=> Bnegado,
- Puntaje=>ALUS6);
- end Behavioral;
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