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Henry-Galleguillos

Bola8 - ALU de 8 bits

Dec 14th, 2020
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  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3.  
  4. entity Bola8 is
  5.  
  6. Port ( A, B: in std_logic_vector(7 downto 0);
  7. Cin: in std_logic;
  8. Cout: out std_logic;
  9. Bnegado: in std_logic;
  10. Puntos: out std_logic_vector(7 downto 0));
  11.  
  12. signal ALUS0, ALUS1, ALUS2, ALUS3, ALUS4, ALUS5, ALUS6, ALUS7: std_logic;
  13. signal Co0, Co1, Co2, Co3, Co4, Co5, Co6, Co7: std_logic;
  14.  
  15. end Bola8;
  16.  
  17. architecture Behavioral of Bola8 is
  18.  
  19. component ALUS
  20. Port ( A,B: in std_logic;
  21. Cin: in std_logic;
  22. Cout: out std_logic;
  23. Bnegado: in std_logic;
  24. Puntaje: out std_logic);
  25. end component;
  26. begin
  27.  
  28. Puntos <= ALUS7 & ALUS6 & ALUS5 & ALUS4 & ALUS3 & ALUS2 & ALUS1 & ALUS0;
  29.  
  30. A0: ALUS port map ( A=> A(0), B=> B(0),
  31. Cin=>Cin, Cout=>Co0,
  32. Bnegado=> Bnegado,
  33. Puntaje=>ALUS0);
  34.  
  35. A1: ALUS port map ( A=> A(1), B=> B(1),
  36. Cin=>Co0, Cout=>Co1,
  37. Bnegado=> Bnegado,
  38. Puntaje=>ALUS1);
  39.  
  40. A2: ALUS port map ( A=> A(2), B=> B(2),
  41. Cin=>Co1, Cout=>Co2,
  42. Bnegado=> Bnegado,
  43. Puntaje=>ALUS2);
  44.  
  45. A3: ALUS port map ( A=> A(3), B=> B(3),
  46. Cin=>Co2, Cout=>Co3,
  47. Bnegado=> Bnegado,
  48. Puntaje=>ALUS3);
  49.  
  50. A4: ALUS port map ( A=> A(4), B=> B(4),
  51. Cin=>Co3, Cout=>Co4,
  52. Bnegado=> Bnegado,
  53. Puntaje=>ALUS4);
  54.  
  55. A5: ALUS port map ( A=> A(5), B=> B(5),
  56. Cin=>Co4, Cout=>Co5,
  57. Bnegado=> Bnegado,
  58. Puntaje=>ALUS5);
  59.  
  60. A6: ALUS port map ( A=> A(6), B=> B(6),
  61. Cin=>Co5, Cout=>Co6,
  62. Bnegado=> Bnegado,
  63. Puntaje=>ALUS6);
  64.  
  65. A7: ALUS port map ( A=> A(7), B=> B(7),
  66. Cin=>Co6, Cout=>Cout,
  67. Bnegado=> Bnegado,
  68. Puntaje=>ALUS6);
  69.  
  70. end Behavioral;
  71.  
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