`timescale 1ns / 1ps
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// Company:
// Engineer:
//
// Create Date: 02/21/2019 03:24:52 PM
// Design Name:
// Module Name: hellokhang
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
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module hellokhang(input [15:0] sw, input CLOCK, output [3:0] an, output reg [7:0] seg = 8'b10001001);

    assign an =       4'b0110;
    parameter [7:0] A =     8'b10001000;
    parameter [7:0] E =     8'b10000110;
    parameter [7:0] G =     8'b10010000;
    parameter [7:0] HK =    8'b10001001;
    parameter [7:0] L =     8'b11000111;
    parameter [7:0] N =     8'b10101011;
    parameter [7:0] O =     8'b11000000;
    parameter [7:0] dash =  8'b10111111;
    parameter [7:0] blank = 8'b01111111;
    reg[27:0] count = 0;
    wire toggle;
    reg switch = 0;
    reg[4:0] next = 0;
    assign toggle = sw[3] ? count[25]:count[27];

    always@ (posedge CLOCK) begin
        case(switch)
            1'b1:
            begin
                next <= (sw[15] == 0)? (next == 11 && sw[2] == 0) ? 0 : ((sw[2] == 0) ? next + 1: ((next == 0) ? 11 : next - 1)) : next;
                count <= 0;
                switch <=0;
            end
            1'b0:
            begin
                count <= count + 1;
                switch <= (toggle == 1) ? 1 : 0;
                case (next)
                    4'b0000:seg <= HK;
                    4'b0001:seg <= E;
                    4'b0010:seg <= L;
                    4'b0011:seg <= L;
                    4'b0100:seg <= O;
                    4'b0101:seg <= dash;
                    4'b0110:seg <= HK;
                    4'b0111:seg <= HK;
                    4'b1000:seg <= A;
                    4'b1001:seg <= N;
                    4'b1010:seg <= G;
                    4'b1011:seg <= blank;
                endcase
            end
      endcase
    end
endmodule