library ieee;
use ieee.std_logic_1164.all;

entity add_sub_4bit is

	port
	(
		-- Input ports
		a	: in  std_logic_vector(3 downto 0);
		b 	: in  std_logic_vector(3 downto 0);
	   sel : in  std_logic;--add if 0 sub if 1


		-- Output ports
		s	: out std_logic_vector(3 downto 0);
		zero	: out std_logic
	);
end add_sub_4bit;



architecture add_sub_arc of add_sub_4bit is

component adder_4bit is

	port
	(
		-- Input ports
		a	: in  std_logic_vector(3 downto 0);
		b 	: in  std_logic_vector(3 downto 0);
	   cin : in  std_logic;


		-- Output ports
		s	: out std_logic_vector(3 downto 0);
		cout	: out std_logic
	);
end component;

signal not_b: std_logic_vector(3 downto 0);
signal mux_out: std_logic_vector(3 downto 0);
signal s_help: std_logic_vector(3 downto 0);


begin

	ADDER4BIT: adder_4bit port map(
	a=>a,
	b=>mux_out,
	cin=>sel,
	s=>s,
	s=>s_help;
	cout=> open
	);


	mux: process(b,not_b,sel) is   --da bi jednom signalu dodelili vrednost na vise mesta u kodu,ovo su ulazi u kombinacioni proces
	begin                            --ako se neki od njih promeni doci ce do promene u kodu , ako ih ne stavimo onda nece

	if (sel='0') then
	mux_out<=b;
	else
	mux_out<=not_b;                   --svaki if mora da ima else!!!
	end if;
   end process mux;


	not_b<=not b;

	zero<= '1' when (s_help=="0000") else '0';  --kraci if, s je def kao izlaz log kola pa nam nije dozvoljeno da ga koristimo ko ulaz u nekoj logici ! ne moze s=="0000" vec s_help

end