Ananya Johnson

`timescale 1ns / 1ps

module myClock( input clk, input rst, output reg out_clk
    );
parameter N = 13000000;

reg [21:0] count;

always@(posedge clk) begin

    if (~rst) begin
    count = 0;
    out_clk = 0;
    end

    else begin
    count = count + 1;
    end

    if (count == N) begin
    count = 0;
    out_clk = ~out_clk;
    end
end

endmodule

module johnson(input clk, input rst, output reg [3:0] x, output reg [6:0] y);

reg [3:0] counter;
wire out_clk;
myClock my(clk,rst,out_clk);

always@(posedge out_clk) begin
    if(~rst) begin
        counter = 0;
        x = 4'b1110;
        y = 7'b0000001;
    end

    else begin
        counter = {counter[2:0],~counter[3]};
        x = {x[2:0],x[3]};
    end

    case (counter)
    0:y = 7'b0000001;
    1:y = 7'b1001111;
    3:y = 7'b0000110;
    7:y = 7'b0001111;
    14:y = 7'b0110000;
    12:y = 7'b0110001;
    8:y = 7'b0000000;
    endcase

end

endmodule

//////////////////////////////////////////////

NET "clk" LOC = "P51";
NET "rst" LOC = "P141";

NET "y[6]" LOC="P140";
NET "y[5]" LOC="P137";
NET "y[4]" LOC="P134";
NET "y[3]" LOC="P133";
NET "y[2]" LOC="P131";
NET "y[1]" LOC="P127";
NET "y[0]" LOC="P126";
NET "x[0]" LOC ="P120";
NET "x[1]" LOC ="P119";
NET "x[2]" LOC ="P118";
NET "x[3]" LOC ="P117";