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- module DualClockDivider(
- input wire iReset,
- input wire iClock,
- output bit oClockA,
- output bit oClockB);
- parameter CLOCK_OUT_A = 64'd15;
- parameter CLOCK_OUT_B = 64'd1;
- parameter CLOCK_INPUT = 64'd100000000;
- parameter CLOCK_DIV_A = CLOCK_INPUT / (CLOCK_OUT_A*64'd2);
- parameter CLOCK_DIV_B = CLOCK_INPUT / (CLOCK_OUT_B*64'd2);
- bit [63:0] mTimeoutA = CLOCK_DIV_A;
- bit [63:0] mTimeoutB = CLOCK_DIV_B;
- bit mStateA = '0;
- bit mStateB = '0;
- assign oClockA = mStateA;
- assign oClockB = mStateB;
- always @(posedge iClock)
- begin
- if (iReset == '0)
- begin
- mTimeoutA <= CLOCK_DIV_A;
- mTimeoutB <= CLOCK_DIV_B;
- mStateA <= '0;
- mStateB <= '0;
- end
- else begin
- if (mTimeoutA == 64'd0) begin
- mStateA <= ~mStateA;
- mTimeoutA <= CLOCK_DIV_A;
- end
- else begin
- mTimeoutA <= mTimeoutA - 64'd1;
- end
- if (mTimeoutB == 64'd0) begin
- mStateB <= ~mStateB;
- mTimeoutB <= CLOCK_DIV_B;
- end
- else begin
- mTimeoutB <= mTimeoutB - 64'd1;
- end
- end
- end
- endmodule
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