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  1. module CamSetup(clk, ready, error, scl, sda);
  2. input clk;
  3. output ready, error;
  4. output scl;
  5. inout sda;
  6.  
  7. parameter ST_READY = 4'd1;
  8. parameter ST_WRITING = 4'd2;
  9. parameter ST_ENDING = 4'd3;
  10. parameter ST_INTERIM = 4'd4;
  11. parameter ST_INITIALWAIT = 4'd0;
  12.  
  13. parameter REG_COUNT = 1;
  14.  
  15. //truncated to save space (actually updates 170 registers)
  16. bit [1:REG_COUNT][0:2][7:0] RegValues = {
  17.     8'h42, 8'h7a, 8'h20
  18. };
  19.  
  20. parameter CLKS_INIT = 10;
  21. parameter CLKS_INTERIM = 50000;
  22.  
  23. reg [23:0] InitiCounter = 0;
  24. reg [23:0] InterimCounter = 0;
  25.  
  26. reg [3:0] State = ST_INITIALWAIT;
  27. reg [7:0] RegIndex  = 0;
  28. reg [2:0] RegByteIndex  = 0;
  29. reg [7:0] WrData = 0;
  30.  
  31. wire WrDataRq;
  32. wire I2cIdle;
  33. wire Enable = (State == ST_WRITING);
  34. assign ready = (State == ST_READY);
  35.  
  36.  
  37. i2c i2c0(.clk(clk), .enable(Enable), .wr_data(WrData), .wr_data_rq(WrDataRq), .idle(I2cIdle), .error(error), .scl(scl), .sda(sda));
  38.  
  39. always @(posedge clk)
  40. begin
  41.  
  42.     case(State)
  43.  
  44.     ST_INITIALWAIT:
  45.     begin
  46.         InitiCounter <= InitiCounter + 1;
  47.  
  48.         if(InitiCounter >= CLKS_INIT)
  49.         begin
  50.             State <= ST_ENDING;
  51.         end    
  52.     end
  53.  
  54.     ST_ENDING:
  55.     begin
  56.         if(I2cIdle)
  57.         begin          
  58.             if(RegIndex < REG_COUNT)
  59.             begin
  60.                 RegIndex <= RegIndex + 1;
  61.                 RegByteIndex <= 0;              
  62.                 WrData <= RegValues[RegIndex+1][0];
  63.                 State <= ST_INTERIM;
  64.             end
  65.             else
  66.             begin
  67.                 State <= ST_READY;
  68.             end        
  69.         end
  70.     end
  71.  
  72.     ST_INTERIM:
  73.     begin
  74.         InterimCounter <= InterimCounter + 1;
  75.  
  76.         if(InterimCounter >= CLKS_INTERIM)
  77.         begin
  78.             InterimCounter <= 0;
  79.             State <= ST_WRITING;
  80.         end
  81.     end
  82.  
  83.     ST_WRITING:
  84.     if(WrDataRq)
  85.     begin      
  86.         if(RegByteIndex < 2)
  87.         begin
  88.             RegByteIndex <= RegByteIndex + 1;
  89.             WrData <= RegValues[RegIndex][RegByteIndex+1];
  90.         end
  91.         else
  92.         begin
  93.             State <= ST_ENDING;
  94.         end
  95.     end        
  96.  
  97.     endcase
  98.  
  99. end
  100.  
  101. endmodule
  102.    
  103. initial begin
  104.     State = non_zero_state;
  105.     ...
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