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  1. commit a2c292da7167cf750c35cc04ebf5a2dbb6da432f
  2. Author: Jens Axboe <axboe@kernel.dk>
  3. Date:   Sat Feb 12 11:42:03 2022 -0700
  4.  
  5.     Add 6001 cpufreq
  6.    
  7.     Signed-off-by: Jens Axboe <axboe@kernel.dk>
  8.  
  9. diff --git a/arch/arm64/boot/dts/apple/t6001.dtsi b/arch/arm64/boot/dts/apple/t6001.dtsi
  10. index 2880c20479f4..7af95ce10215 100644
  11. --- a/arch/arm64/boot/dts/apple/t6001.dtsi
  12. +++ b/arch/arm64/boot/dts/apple/t6001.dtsi
  13. @@ -24,84 +24,315 @@ cpus {
  14.         #address-cells = <2>;
  15.         #size-cells = <0>;
  16.  
  17. -       cpu0: cpu@0 {
  18. +       cpu-map {
  19. +           cluster0 {
  20. +               core0 {
  21. +                   cpu = <&cpu_e0>;
  22. +               };
  23. +               core1 {
  24. +                   cpu = <&cpu_e1>;
  25. +               };
  26. +           };
  27. +
  28. +           cluster1 {
  29. +               core0 {
  30. +                   cpu = <&cpu_p0>;
  31. +               };
  32. +               core1 {
  33. +                   cpu = <&cpu_p1>;
  34. +               };
  35. +               core2 {
  36. +                   cpu = <&cpu_p2>;
  37. +               };
  38. +               core3 {
  39. +                   cpu = <&cpu_p3>;
  40. +               };
  41. +           };
  42. +
  43. +           cluster2 {
  44. +               core0 {
  45. +                   cpu = <&cpu_p4>;
  46. +               };
  47. +               core1 {
  48. +                   cpu = <&cpu_p5>;
  49. +               };
  50. +               core2 {
  51. +                   cpu = <&cpu_p6>;
  52. +               };
  53. +               core3 {
  54. +                   cpu = <&cpu_p7>;
  55. +               };
  56. +           };
  57. +       };
  58. +
  59. +       cpu_e0: cpu@0 {
  60.             compatible = "apple,icestorm";
  61.             device_type = "cpu";
  62.             reg = <0x0 0x0>;
  63.             enable-method = "spin-table";
  64.             cpu-release-addr = <0 0>; /* To be filled by loader */
  65. +           clocks = <&clk_ecluster>;
  66. +           operating-points-v2 = <&ecluster_opp>;
  67. +           capacity-dmips-mhz = <714>;
  68.         };
  69.  
  70. -       cpu1: cpu@1 {
  71. +       cpu_e1: cpu@1 {
  72.             compatible = "apple,icestorm";
  73.             device_type = "cpu";
  74.             reg = <0x0 0x1>;
  75.             enable-method = "spin-table";
  76.             cpu-release-addr = <0 0>; /* To be filled by loader */
  77. +           clocks = <&clk_ecluster>;
  78. +           operating-points-v2 = <&ecluster_opp>;
  79. +           capacity-dmips-mhz = <714>;
  80.         };
  81.  
  82. -       cpu2: cpu@10100 {
  83. +       cpu_p0: cpu@10100 {
  84.             compatible = "apple,firestorm";
  85.             device_type = "cpu";
  86.             reg = <0x0 0x10100>;
  87.             enable-method = "spin-table";
  88.             cpu-release-addr = <0 0>; /* To be filled by loader */
  89. +           clocks = <&clk_pcluster0>;
  90. +           operating-points-v2 = <&pcluster_opp>;
  91. +           capacity-dmips-mhz = <1024>;
  92.         };
  93.  
  94. -       cpu3: cpu@10101 {
  95. +       cpu_p1: cpu@10101 {
  96.             compatible = "apple,firestorm";
  97.             device_type = "cpu";
  98.             reg = <0x0 0x10101>;
  99.             enable-method = "spin-table";
  100.             cpu-release-addr = <0 0>; /* To be filled by loader */
  101. +           clocks = <&clk_pcluster0>;
  102. +           operating-points-v2 = <&pcluster_opp>;
  103. +           capacity-dmips-mhz = <1024>;
  104.         };
  105.  
  106. -       cpu4: cpu@10102 {
  107. +       cpu_p2: cpu@10102 {
  108.             compatible = "apple,firestorm";
  109.             device_type = "cpu";
  110.             reg = <0x0 0x10102>;
  111.             enable-method = "spin-table";
  112.             cpu-release-addr = <0 0>; /* To be filled by loader */
  113. +           clocks = <&clk_pcluster0>;
  114. +           operating-points-v2 = <&pcluster_opp>;
  115. +           capacity-dmips-mhz = <1024>;
  116.         };
  117.  
  118. -       cpu5: cpu@10103 {
  119. +       cpu_p3: cpu@10103 {
  120.             compatible = "apple,firestorm";
  121.             device_type = "cpu";
  122.             reg = <0x0 0x10103>;
  123.             enable-method = "spin-table";
  124.             cpu-release-addr = <0 0>; /* To be filled by loader */
  125. +           clocks = <&clk_pcluster0>;
  126. +           operating-points-v2 = <&pcluster_opp>;
  127. +           capacity-dmips-mhz = <1024>;
  128.         };
  129.  
  130. -       cpu6: cpu@10200 {
  131. +       cpu_p4: cpu@10200 {
  132.             compatible = "apple,firestorm";
  133.             device_type = "cpu";
  134.             reg = <0x0 0x10200>;
  135.             enable-method = "spin-table";
  136.             cpu-release-addr = <0 0>; /* To be filled by loader */
  137. +           clocks = <&clk_pcluster1>;
  138. +           operating-points-v2 = <&pcluster_opp>;
  139. +           capacity-dmips-mhz = <1024>;
  140.         };
  141.  
  142. -       cpu7: cpu@10201 {
  143. +       cpu_p5: cpu@10201 {
  144.             compatible = "apple,firestorm";
  145.             device_type = "cpu";
  146.             reg = <0x0 0x10201>;
  147.             enable-method = "spin-table";
  148.             cpu-release-addr = <0 0>; /* To be filled by loader */
  149. +           clocks = <&clk_pcluster1>;
  150. +           operating-points-v2 = <&pcluster_opp>;
  151. +           capacity-dmips-mhz = <1024>;
  152.         };
  153.  
  154. -       cpu8: cpu@10202 {
  155. +       cpu_p6: cpu@10202 {
  156.             compatible = "apple,firestorm";
  157.             device_type = "cpu";
  158.             reg = <0x0 0x10202>;
  159.             enable-method = "spin-table";
  160.             cpu-release-addr = <0 0>; /* To be filled by loader */
  161. +           clocks = <&clk_pcluster1>;
  162. +           operating-points-v2 = <&pcluster_opp>;
  163. +           capacity-dmips-mhz = <1024>;
  164.         };
  165.  
  166. -       cpu9: cpu@10203 {
  167. +       cpu_p7: cpu@10203 {
  168.             compatible = "apple,firestorm";
  169.             device_type = "cpu";
  170.             reg = <0x0 0x10203>;
  171.             enable-method = "spin-table";
  172.             cpu-release-addr = <0 0>; /* To be filled by loader */
  173. +           clocks = <&clk_pcluster1>;
  174. +           operating-points-v2 = <&pcluster_opp>;
  175. +           capacity-dmips-mhz = <1024>;
  176. +       };
  177. +   };
  178. +
  179. +   ecluster_opp: opp-table-0 {
  180. +       compatible = "operating-points-v2";
  181. +       opp-shared;
  182. +
  183. +       opp01 {
  184. +           opp-hz = /bits/ 64 <600000000>;
  185. +           opp-microvolt = <559000>;
  186. +           opp-level = <1>;
  187. +           clock-latency-ns = <7500>;
  188. +       };
  189. +       opp02 {
  190. +           opp-hz = /bits/ 64 <972000000>;
  191. +           opp-microvolt = <628000>;
  192. +           opp-level = <2>;
  193. +           clock-latency-ns = <22000>;
  194. +       };
  195. +       opp03 {
  196. +           opp-hz = /bits/ 64 <1332000000>;
  197. +           opp-microvolt = <684000>;
  198. +           opp-level = <3>;
  199. +           clock-latency-ns = <27000>;
  200. +       };
  201. +       opp04 {
  202. +           opp-hz = /bits/ 64 <1704000000>;
  203. +           opp-microvolt = <765000>;
  204. +           opp-level = <4>;
  205. +           clock-latency-ns = <33000>;
  206. +       };
  207. +       opp05 {
  208. +           opp-hz = /bits/ 64 <2064000000>;
  209. +           opp-microvolt = <868000>;
  210. +           opp-level = <5>;
  211. +           clock-latency-ns = <50000>;
  212. +       };
  213. +   };
  214. +
  215. +   pcluster_opp: opp-table-1 {
  216. +       compatible = "operating-points-v2";
  217. +       opp-shared;
  218. +
  219. +       opp01 {
  220. +           opp-hz = /bits/ 64 <600000000>;
  221. +           opp-microvolt = <781000>;
  222. +           opp-level = <1>;
  223. +           clock-latency-ns = <8000>;
  224. +           required-opps = <&mcc_lowperf>;
  225. +       };
  226. +       opp02 {
  227. +           opp-hz = /bits/ 64 <828000000>;
  228. +           opp-microvolt = <781000>;
  229. +           opp-level = <2>;
  230. +           clock-latency-ns = <19000>;
  231. +           required-opps = <&mcc_lowperf>;
  232. +       };
  233. +       opp03 {
  234. +           opp-hz = /bits/ 64 <1056000000>;
  235. +           opp-microvolt = <781000>;
  236. +           opp-level = <3>;
  237. +           clock-latency-ns = <21000>;
  238. +           required-opps = <&mcc_lowperf>;
  239. +       };
  240. +       opp04 {
  241. +           opp-hz = /bits/ 64 <1284000000>;
  242. +           opp-microvolt = <800000>;
  243. +           opp-level = <4>;
  244. +           clock-latency-ns = <23000>;
  245. +           required-opps = <&mcc_lowperf>;
  246. +       };
  247. +       opp05 {
  248. +           opp-hz = /bits/ 64 <1500000000>;
  249. +           opp-microvolt = <821000>;
  250. +           opp-level = <5>;
  251. +           clock-latency-ns = <24000>;
  252. +           required-opps = <&mcc_lowperf>;
  253. +       };
  254. +       opp06 {
  255. +           opp-hz = /bits/ 64 <1728000000>;
  256. +           opp-microvolt = <831000>;
  257. +           opp-level = <6>;
  258. +           clock-latency-ns = <29000>;
  259. +           required-opps = <&mcc_lowperf>;
  260. +       };
  261. +       opp07 {
  262. +           opp-hz = /bits/ 64 <1956000000>;
  263. +           opp-microvolt = <865000>;
  264. +           opp-level = <7>;
  265. +           clock-latency-ns = <31000>;
  266. +           required-opps = <&mcc_lowperf>;
  267. +       };
  268. +       opp08 {
  269. +           opp-hz = /bits/ 64 <2184000000>;
  270. +           opp-microvolt = <909000>;
  271. +           opp-level = <8>;
  272. +           clock-latency-ns = <34000>;
  273. +           required-opps = <&mcc_highperf>;
  274. +       };
  275. +       opp09 {
  276. +           opp-hz = /bits/ 64 <2388000000>;
  277. +           opp-microvolt = <953000>;
  278. +           opp-level = <9>;
  279. +           clock-latency-ns = <36000>;
  280. +           required-opps = <&mcc_highperf>;
  281. +       };
  282. +       opp10 {
  283. +           opp-hz = /bits/ 64 <2592000000>;
  284. +           opp-microvolt = <1003000>;
  285. +           opp-level = <10>;
  286. +           clock-latency-ns = <51000>;
  287. +           required-opps = <&mcc_highperf>;
  288. +       };
  289. +       opp11 {
  290. +           opp-hz = /bits/ 64 <2772000000>;
  291. +           opp-microvolt = <1053000>;
  292. +           opp-level = <11>;
  293. +           clock-latency-ns = <54000>;
  294. +           required-opps = <&mcc_highperf>;
  295. +       };
  296. +       opp12 {
  297. +           opp-hz = /bits/ 64 <2988000000>;
  298. +           opp-microvolt = <1081000>;
  299. +           opp-level = <12>;
  300. +           clock-latency-ns = <55000>;
  301. +           required-opps = <&mcc_highperf>;
  302. +       };
  303. +       opp13 {
  304. +           opp-hz = /bits/ 64 <3096000000>;
  305. +           opp-microvolt = <1081000>;
  306. +           opp-level = <13>;
  307. +           clock-latency-ns = <55000>;
  308. +           required-opps = <&mcc_highperf>;
  309. +       };
  310. +       opp14 {
  311. +           opp-hz = /bits/ 64 <3144000000>;
  312. +           opp-microvolt = <1081000>;
  313. +           opp-level = <14>;
  314. +           clock-latency-ns = <56000>;
  315. +           required-opps = <&mcc_highperf>;
  316. +       };
  317. +       opp15 {
  318. +           opp-hz = /bits/ 64 <3204000000>;
  319. +           opp-microvolt = <1081000>;
  320. +           opp-level = <15>;
  321. +           clock-latency-ns = <56000>;
  322. +           required-opps = <&mcc_highperf>;
  323. +       };
  324. +   };
  325. +
  326. +   mcc_opp: opp-table-2 {
  327. +       compatible = "apple,mcc-operating-points";
  328. +
  329. +       mcc_lowperf: opp0 {
  330. +           opp-level = <0>;
  331. +           apple,memory-perf-config = <0x813057f 0x1800180>;
  332. +       };
  333. +       mcc_highperf: opp1 {
  334. +           opp-level = <1>;
  335. +           apple,memory-perf-config = <0x133 0x55555340>;
  336.         };
  337.     };
  338.  
  339. @@ -491,6 +722,37 @@ spi3: spi@39b10c000 {
  340.             status = "disabled";
  341.         };
  342.  
  343. +       mcc: memory-controller@200200000 {
  344. +           compatible = "apple,t6101-mcc", "apple,mcc";
  345. +           #power-domain-cells = <0>;
  346. +           reg = <0x2 0x200000 0x0 0x200000>;
  347. +           operating-points-v2 = <&mcc_opp>;
  348. +           apple,num-channels = <8>;
  349. +       };
  350. +
  351. +       clk_ecluster: clock-controller@210e20000 {
  352. +           compatible = "apple,t6101-cluster-clk", "apple,cluster-clk";
  353. +           #clock-cells = <0>;
  354. +           reg = <0x2 0x10e20000 0x0 0x4000>;
  355. +           operating-points-v2 = <&ecluster_opp>;
  356. +       };
  357. +
  358. +       clk_pcluster0: clock-controller@211e20000 {
  359. +           compatible = "apple,t6101-cluster-clk", "apple,cluster-clk";
  360. +           #clock-cells = <0>;
  361. +           reg = <0x2 0x11e20000 0x0 0x4000>;
  362. +           operating-points-v2 = <&pcluster_opp>;
  363. +           power-domains = <&mcc>;
  364. +       };
  365. +
  366. +       clk_pcluster1: clock-controller@212e20000 {
  367. +           compatible = "apple,t6101-cluster-clk", "apple,cluster-clk";
  368. +           #clock-cells = <0>;
  369. +           reg = <0x2 0x12e20000 0x0 0x4000>;
  370. +           operating-points-v2 = <&pcluster_opp>;
  371. +           power-domains = <&mcc>;
  372. +       };
  373. +
  374.         serial0: serial@39b200000 {
  375.             compatible = "apple,s5l-uart";
  376.             reg = <0x3 0x9b200000 0x0 0x1000>;
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