module top(
    output wire [5:0] out_io,
    input  wire clk_in
);

    wire clk;
    reg [15:0] cnt;

    SB_GB clk_gbuf_I (
        .USER_SIGNAL_TO_GLOBAL_BUFFER(clk_48m),
        .GLOBAL_BUFFER_OUTPUT(clk)
    );


    genvar i;
    generate

        for (i=0; i<6; i=i+1)
            SB_IO #(
                .PIN_TYPE(6'b110100),
                .PULLUP(1'b0),
                .NEG_TRIGGER(1'b0),
                .IO_STANDARD("SB_LVCMOS")
            ) io_I (
                .PACKAGE_PIN(out_io[i]),
                .LATCH_INPUT_VALUE(1'b0),
                .CLOCK_ENABLE(1'b1),
                .INPUT_CLK(1'b0),
                .OUTPUT_CLK(clk),
                .OUTPUT_ENABLE(cnt[i]),
                .D_OUT_0(cnt[i+1]),
                .D_OUT_1(1'b0),
                .D_IN_0(),
                .D_IN_1()
            );

    endgenerate

    always @(posedge clk)
        cnt <= cnt + 1;

endmodule