Advertisement
Guest User

Untitled

a guest
Oct 24th, 2018
156
0
Never
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
text 0.93 KB | None | 0 0
  1. module top(
  2. output wire [5:0] out_io,
  3. input wire clk_in
  4. );
  5.  
  6. wire clk;
  7. reg [15:0] cnt;
  8.  
  9. SB_GB clk_gbuf_I (
  10. .USER_SIGNAL_TO_GLOBAL_BUFFER(clk_48m),
  11. .GLOBAL_BUFFER_OUTPUT(clk)
  12. );
  13.  
  14.  
  15. genvar i;
  16. generate
  17.  
  18. for (i=0; i<6; i=i+1)
  19. SB_IO #(
  20. .PIN_TYPE(6'b110100),
  21. .PULLUP(1'b0),
  22. .NEG_TRIGGER(1'b0),
  23. .IO_STANDARD("SB_LVCMOS")
  24. ) io_I (
  25. .PACKAGE_PIN(out_io[i]),
  26. .LATCH_INPUT_VALUE(1'b0),
  27. .CLOCK_ENABLE(1'b1),
  28. .INPUT_CLK(1'b0),
  29. .OUTPUT_CLK(clk),
  30. .OUTPUT_ENABLE(cnt[i]),
  31. .D_OUT_0(cnt[i+1]),
  32. .D_OUT_1(1'b0),
  33. .D_IN_0(),
  34. .D_IN_1()
  35. );
  36.  
  37. endgenerate
  38.  
  39. always @(posedge clk)
  40. cnt <= cnt + 1;
  41.  
  42. endmodule
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement