Info: Critical path report for clock 'clk_$glb_clk' (posedge -> posedge):
Info: curr total
Info:  1.4  2.8  Source $abc$1839$auto$blifparse.cc:492:parse_blif$1883_LC.O
Info:  1.8  4.5    Net reg_flags[0] budget -3.322000 ns (15,12) -> (14,12)
Info:                Sink $abc$1839$auto$blifparse.cc:492:parse_blif$1925_LC.I1
Info:  1.2  5.8  Source $abc$1839$auto$blifparse.cc:492:parse_blif$1925_LC.O
Info:  1.8  7.5    Net ex_cc_match budget -2.211000 ns (14,12) -> (13,11)
Info:                Sink $abc$1839$auto$blifparse.cc:492:parse_blif$1887_LC.I3
Info:  0.9  8.4  Source $abc$1839$auto$blifparse.cc:492:parse_blif$1887_LC.O
Info:  1.8 10.2    Net pma_op_mux[0] budget -1.995000 ns (13,11) -> (13,12)
Info:                Sink $auto$alumacc.cc:474:replace_alu$141.slice[0].carry$CARRY.I2
Info:  0.6 10.8  Source $auto$alumacc.cc:474:replace_alu$141.slice[0].carry$CARRY.COUT
Info:  0.0 10.8    Net $auto$alumacc.cc:474:replace_alu$141.C[1] budget 0.000000 ns (13,12) -> (13,12)
Info:                Sink $auto$alumacc.cc:474:replace_alu$141.slice[1].adder_LC.CIN
Info:  0.3 11.1  Source $auto$alumacc.cc:474:replace_alu$141.slice[1].adder_LC.COUT
Info:  0.0 11.1    Net $auto$alumacc.cc:474:replace_alu$141.C[2] budget 0.000000 ns (13,12) -> (13,12)
Info:                Sink $auto$alumacc.cc:474:replace_alu$141.slice[2].adder_LC.CIN
Info:  0.3 11.3  Source $auto$alumacc.cc:474:replace_alu$141.slice[2].adder_LC.COUT
Info:  0.0 11.3    Net $auto$alumacc.cc:474:replace_alu$141.C[3] budget 0.000000 ns (13,12) -> (13,12)
Info:                Sink $auto$alumacc.cc:474:replace_alu$141.slice[3].adder_LC.CIN
Info:  0.3 11.6  Source $auto$alumacc.cc:474:replace_alu$141.slice[3].adder_LC.COUT
Info:  0.0 11.6    Net $auto$alumacc.cc:474:replace_alu$141.C[4] budget 0.000000 ns (13,12) -> (13,12)
Info:                Sink $auto$alumacc.cc:474:replace_alu$141.slice[4].adder_LC.CIN
Info:  0.3 11.9  Source $auto$alumacc.cc:474:replace_alu$141.slice[4].adder_LC.COUT
Info:  0.0 11.9    Net $auto$alumacc.cc:474:replace_alu$141.C[5] budget 0.000000 ns (13,12) -> (13,12)
Info:                Sink $auto$alumacc.cc:474:replace_alu$141.slice[5].adder_LC.CIN
Info:  0.3 12.2  Source $auto$alumacc.cc:474:replace_alu$141.slice[5].adder_LC.COUT
Info:  0.0 12.2    Net $auto$alumacc.cc:474:replace_alu$141.C[6] budget 0.000000 ns (13,12) -> (13,12)
Info:                Sink $auto$alumacc.cc:474:replace_alu$141.slice[6].adder_LC.CIN
Info:  0.3 12.4  Source $auto$alumacc.cc:474:replace_alu$141.slice[6].adder_LC.COUT
Info:  0.0 12.4    Net $auto$alumacc.cc:474:replace_alu$141.C[7] budget 0.000000 ns (13,12) -> (13,12)
Info:                Sink $auto$alumacc.cc:474:replace_alu$141.slice[7].adder_LC.CIN
Info:  0.3 12.7  Source $auto$alumacc.cc:474:replace_alu$141.slice[7].adder_LC.COUT
Info:  0.6 13.3    Net $auto$alumacc.cc:474:replace_alu$141.C[8] budget 0.560000 ns (13,12) -> (13,13)
Info:                Sink $auto$alumacc.cc:474:replace_alu$141.slice[8].adder_LC.CIN
Info:  0.3 13.6  Source $auto$alumacc.cc:474:replace_alu$141.slice[8].adder_LC.COUT
Info:  0.0 13.6    Net $auto$alumacc.cc:474:replace_alu$141.C[9] budget 0.000000 ns (13,13) -> (13,13)
Info:                Sink $auto$alumacc.cc:474:replace_alu$141.slice[9].adder_LC.CIN
Info:  0.3 13.8  Source $auto$alumacc.cc:474:replace_alu$141.slice[9].adder_LC.COUT
Info:  0.0 13.8    Net $auto$alumacc.cc:474:replace_alu$141.C[10] budget 0.000000 ns (13,13) -> (13,13)
Info:                Sink $auto$alumacc.cc:474:replace_alu$141.slice[10].adder_LC.CIN
Info:  0.3 14.1  Source $auto$alumacc.cc:474:replace_alu$141.slice[10].adder_LC.COUT
Info:  0.0 14.1    Net $auto$alumacc.cc:474:replace_alu$141.C[11] budget 0.000000 ns (13,13) -> (13,13)
Info:                Sink $auto$alumacc.cc:474:replace_alu$141.slice[11].adder_LC.CIN
Info:  0.3 14.4  Source $auto$alumacc.cc:474:replace_alu$141.slice[11].adder_LC.COUT
Info:  0.0 14.4    Net $auto$alumacc.cc:474:replace_alu$141.C[12] budget 0.000000 ns (13,13) -> (13,13)
Info:                Sink $auto$alumacc.cc:474:replace_alu$141.slice[12].adder_LC.CIN
Info:  0.3 14.7  Source $auto$alumacc.cc:474:replace_alu$141.slice[12].adder_LC.COUT
Info:  0.7 15.3    Net $auto$alumacc.cc:474:replace_alu$141.C[13] budget -2.755000 ns (13,13) -> (13,13)
Info:                Sink $auto$alumacc.cc:474:replace_alu$141.slice[13].adder_LC.I3
Info:  0.0 15.3  Source $auto$alumacc.cc:474:replace_alu$141.slice[13].adder_LC.O
Info:  5.3 20.7    Net pram_addr[13] budget 0.933000 ns (13,13) -> (25,0)
Info:                Sink pram_I_RAM.ADDRESS_13
Info:  0.1 20.8  Setup pram_I_RAM.ADDRESS_13
Info: 8.9 ns logic, 11.8 ns routing

Info: Critical path report for cross-domain path '<async>' -> 'posedge clk_$glb_clk':
Info: curr total
Info:  0.0  0.0  Source rst$sb_io.D_IN_0
Info:  1.7  1.7    Net rst budget 8.340000 ns (19,31) -> (19,31)
Info:                Sink $gbuf_rst_$glb_sr.USER_SIGNAL_TO_GLOBAL_BUFFER
Info:  0.0  1.7  Source $gbuf_rst_$glb_sr.GLOBAL_BUFFER_OUTPUT
Info:  0.6  2.4    Net rst_$glb_sr budget 8.601000 ns (19,31) -> (13,11)
Info:                Sink $auto$simplemap.cc:496:simplemap_adff$811_DFFLC.SR
Info:  0.1  2.5  Setup $auto$simplemap.cc:496:simplemap_adff$811_DFFLC.SR
Info: 0.1 ns logic, 2.4 ns routing

Info: Critical path report for cross-domain path 'posedge clk_$glb_clk' -> '<async>':
Info: curr total
Info:  0.0  1.4  Source $abc$1839$auto$blifparse.cc:492:parse_blif$1878_LC.O
Info:  5.5  6.8    Net reg_a[0] budget 23.610001 ns (18,10) -> (18,31)
Info:                Sink dummy$sb_io.D_OUT_0
Info: 1.4 ns logic, 5.5 ns routing

ERROR: Max frequency for clock 'clk_$glb_clk': 39.07 MHz (FAIL at 40.00 MHz)

Info: Max delay <async>              -> posedge clk_$glb_clk: 4.07 ns
Info: Max delay posedge clk_$glb_clk -> <async>             : 6.84 ns