// CAN2_TX SODIMM 94
             IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA = IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA_MUX_MODE(1);
             IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA = IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_PE_MASK |
                                        IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_PS(3)   |
                                        IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_DSE(0)  |
                                        IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_HYS_MASK;

 // CAN2_RX SODIMM 81
             IOMUXC_FLEXCAN2_RX_SELECT_INPUT = 0x0;
             IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL = IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL_MUX_MODE(1);
             IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL = IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_PE_MASK |
                                        IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_PS(3)   |
                                        IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_DSE(0)  |
                                        IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_HYS_MASK;