1012期末懶人包_2

module mod2(input clk_50M, reset, output reg clk_25M);
  always @(posedge clk_50M or negedge reset)
    begin
      if(!reset)
        clk_25M <= 0;
      else
        clk_25M <= ~clk_25M;
    end
endmodule

--------------------------------------------------------------------

module mod4(input clk_50M, reset, output reg clk_25M, clk_12_5M);
 always@(posedge clk_50M or negedge reset)
    begin
      if(!reset)
        clk_25M <= 0;
      else
        clk_25M <= ~clk_25M;
    end
 always@(posedge clk_25M or negedge reset)
    begin
      if(!reset)
        clk_12_5M <= 0;
      else
        clk_12_5M <= ~clk_12_5M;
    end
endmodule

--------------------------------------------------------------------

module FSM_practice(input en,ck,reset,output reg [2:0]state);
parameter A = 3'b000 ,B = 3'b001 ,C = 3'b010 ,D = 3'b011 ,E = 3'b100 ,F = 3'b101 ,G = 3'b110 ;

// 0246135 --> ACEGBDF

always @(posedge ck or posedge reset)
begin
    if(reset) state <= A ;
    else if(~en) state <= state ;
    else
        begin
            case(state)
            A: if(en) state <= C;
            C: if(en) state <= E;
            E: if(en) state <= G;
            G: if(en) state <= B;
            B: if(en) state <= D;
            D: if(en) state <= F;
            F: if(en) state <= A;
            default: state <= A;
            endcase
        end
end
endmodule

---------------------------------------------------------------------

module seg_scan(clk, rst, seg_en, seg);
input  clk, rst;
output [3:0] seg_en;
output [7:0] seg;

wire scan_clk, count_clk;
wire [3:0] scan_code;
reg [31:0] div;
reg [15:0] count;
reg [3:0] seg_en;

always@(posedge clk, negedge rst)
begin
    if(!rst)
      div <= 32'b0;
    else
      div <= div + 1;
end

assign scan_clk  = div[16];  // 約5ms   250Hz scan period 20ms / 4(segs)
assign count_clk = div[17];  // 約10ms  100Hz

always@(posedge scan_clk, negedge rst) //low level to enable seg
begin
    if(!rst)
        seg_en <= 4'b1110 ;
    else
        seg_en <= !seg_en[0]?4'b1101:
                  !seg_en[1]?4'b1011:
                  !seg_en[2]?4'b0111:
                  4'b1110;

        //seg_en <= {seg_en[0] , seg_en[3:1]} ;
end


assign scan_code =  (seg_en == 4'b1110) ? (count[3:0]) :
            (seg_en == 4'b1101) ? (count[7:4]) :
            (seg_en == 4'b1011) ? (count[11:8]) :
                    (count[15:12]) ;

always@(posedge count_clk, negedge rst) //plus 6 to fix the BCD_code
begin
    if(!rst)
        count <= 0 ;
    else if(count[15:12]==9)
        count[15:12] <= count[15:12]+6;
    else if(count[11:8]==9)
        count[12:8] <= count[12:8]+6;
    else if(count[7:4]==9)
        count[8:4] <= count[8:4]+6;
    else if(count[3:0]==9)
        count[4:0] <= count[4:0]+6;
    else
        count <= count+1 ;

end

assign seg = (scan_code==0)?(8'b00000011):
             (scan_code==1)?(8'b10011111):
             (scan_code==2)?(8'b00100101):
             (scan_code==3)?(8'b00001101):
             (scan_code==4)?(8'b10011001):
             (scan_code==5)?(8'b01001001):
             (scan_code==6)?(8'b01000001):
             (scan_code==7)?(8'b00011011):
             (scan_code==8)?(8'b00000001):
             (8'b00001001);

endmodule

--------------------------------------------------------------------------------

module flashlight(input re,ck,L, R, H,output LA, LB, LC, RA, RB, RC);
parameter IDLE = 0 , R1 = 1 , R2 = 2 , R3 = 3 ,
          L1 = 4 , L2 = 5 , L3 = 6 , LR3 = 7 ;
wire scan_clk;
reg [2:0] state;
reg[23:0] div;

always @(posedge ck, negedge re)
    begin
        if(!re)
            begin
                    div <= 24'b0;
            end
        else
            begin
                    div <= div + 1;
            end
    end

assign scan_clk = div[23]; // 0.67s

always @(negedge scan_clk)
begin
    case(state)
    IDLE:if(H|L&R) state <= LR3 ;
         else if(L&~R&~H) state <= L1;
         else if(R&~L&~H) state <= R1;
         else state <= IDLE ;
    L1:  if(H|L&R) state <= LR3 ;
         else   if(L&~R&~H) state <= L2;
         else state <= IDLE ;
    L2:  if(H|L&R) state <= LR3 ;
         else if(L&~R&~H) state <= L3;
         else state <= IDLE ;
    L3:  state <= IDLE ;
    R1:  if(H|L&R) state <= LR3 ;
         else if(R&~L&~H) state <= R2;
         else state <= IDLE ;
    R2:  if(H|L&R) state <= LR3 ;
         else if(R&~L&~H) state <= R3;
         else state <= IDLE ;
    R3:  state <= IDLE ;
    LR3: state <= IDLE ;
    default : state <= IDLE ;
    endcase
end
assign LA = ~((state==L1)|(state==L2)|(state==L3)|(state==LR3));
assign LB = ~((state==L2)|(state==L3)|(state==LR3));
assign LC = ~((state==L3)|(state==LR3));
assign RA = ~((state==R1)|(state==R2)|(state==R3)|(state==LR3));
assign RB = ~((state==R2)|(state==R3)|(state==LR3));
assign RC = ~((state==R3)|(state==LR3));

endmodule