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  1. module ROM_code(out, addr, CS);
  2. output[15:0] out;
  3. input[3:0] addr;
  4. input CS;
  5. reg [15:0] out;
  6. reg [15:0] ROM[15:0];
  7. always @(negedge CS)
  8. begin
  9. ROM[0]=16'h5601; ROM[1]=16'h3401;
  10. ROM[2]=16'h1801; ROM[3]=16'h0ac1;
  11. ROM[4]=16'h0521; ROM[5]=16'h0221;
  12. ROM[6]=16'h5601; ROM[7]=16'h5401;
  13. ROM[8]=16'h4801; ROM[9]=16'h3801;
  14. ROM[10]=16'h3001; ROM[11]=16'h2401;
  15. ROM[12]=16'h1c01; ROM[13]=16'h1601;
  16. ROM[14]=16'h5601; ROM[15]=16'h5401;
  17. out=ROM[addr];
  18. end
  19. endmodule
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