module traffic
(
input wire clk,reset,
output reg[2:0] N,S,E,W
);

localparam[2:0] S0=3'b000,
                S1=3'b001,
					 S2=3'b010,
					 S3=3'b011,
					 S4=3'b100,
					 S5=3'b101,
					 S6=3'b110,
					 S7=3'b111;

reg[2:0]state,next_state;
reg[24:0]count1=0;
reg[24:0]count2=0;
reg count20_en=0,count3_en=0;
reg delay20s=0,delay3s=0;
wire clk_en;

always @(posedge clk,posedge reset)
if(reset)
state <= S0;
else
state <= next_state;

always @*
begin
next_state = state;
N = 0;
E = 0;
S = 0;
W = 0;
case(state)

S0:begin
N=3'b001;
E=3'b100;
S=3'b100;
W=3'b100;
count20_en = 1;
count3_en = 0;
if(delay20s)
next_state = S1;
else
next_state = S0;
end

S1:begin
N=3'b010;
E=3'b010;
S=3'b100;
W=3'b100;
count20_en = 0;
count3_en = 1;
if(delay3s)
next_state = S2;
else
next_state = S1;
end

S2: begin
N = 3'b100;
E = 3'b001;
S = 3'b100;
W = 3'b100;
count20_en = 1;
count3_en = 0;
if(delay20s)
next_state = S3;
else
next_state = S2;
end

S3: begin
N= 3'b100;
E = 3'b010;
S = 3'b010;
W = 3'b100;
count20_en = 0;
count3_en = 1;
if(delay3s)
next_state = S4;
else
next_state = S3;
end

S4: begin
N = 3'b100;
E = 3'b100;
S = 3'b001;
W = 3'b100;
count20_en = 1;
count3_en = 0;
if(delay20s)
next_state = S5;
else
next_state = S4;
end

S5: begin
N = 3'b100;
E = 3'b100;
S = 3'b010;
W = 3'b010;
count20_en = 0;
count3_en = 1;
if(delay3s)
next_state = S6;
else
next_state = S5;
end

S6: begin
N = 3'b100;
E = 3'b100;
S = 3'b100;
W = 3'b001;
count20_en = 1;
count3_en = 0;
if(delay20s)
next_state = S7;
else
next_state = S6;
end

S7: begin
N = 3'b010;
E = 3'b100;
S = 3'b100;
W = 3'b010;
count20_en = 0;
count3_en = 1;
if(delay3s)
next_state = S0;
else
next_state = S7;
end

default: next_state = S0;
endcase
end


always @(posedge clk)
begin
if(clk_en == 1)
begin
if(count20_en || count3_en)
count2 = count2 + 1;
if(count2 == 19 & count20_en)
begin
delay20s = 1;
delay3s = 0;
count2 = 0;
end
else if(count2 == 2 & count3_en)
begin
delay20s  =0;
delay3s = 1;
end
else
begin
delay20s = 0;
delay3s = 0;
end
end
end

always @(posedge clk)
begin
count1 <= count1 + 1;
if(count1 == 3)
count1 <= 0;
end
assign clk_en = (count1 == 3) ? 1 : 0;



endmodule