entity instr_ram is
    Port ( iCLK : in  STD_LOGIC;
           inRST : in  STD_LOGIC;
           iA : in  STD_LOGIC_VECTOR (4 downto 0);
           iD : in  STD_LOGIC_VECTOR (15 downto 0);
           iWE : in  STD_LOGIC;
           oQ : out  STD_LOGIC_VECTOR (15 downto 0));
end instr_ram;

architecture Behavioral of instr_ram is

	type tRAM is array (0 to 31) of STD_LOGIC_VECTOR (15 downto 0);
	signal sRAM: tRAM;

begin

	process (iCLK) begin
		if (iCLK'event and iCLK='1') then
			if (inRST='0') then
				sRAM<=(x"0000",x"0000",x"0000",x"0000",x"0000",x"0000",x"0000",x"0000",x"0000",x"0000",
						x"0000",x"0000",x"0000",x"0000",x"0000",x"0000",x"0000",x"0000",x"0000",x"0000",
						x"0000",x"0000",x"0000",x"0000",x"0000",x"0000",x"0000",x"0000",x"0000",x"0000",
						x"0000",x"0000");
	   else
			if (iWE='1') then
				sRAM(CONV_INTEGER(iA))<=iD;

			end if;
		end if;
	end process;

	oQ<=sRAM(CONV_INTEGER(iA));

end Behavioral;