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Apr 15th, 2013
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  1. from migen.fhdl.structure import *
  2. from migen.fhdl.module import Module
  3. from migen.fhdl import verilog
  4.  
  5. def foo1(x):
  6.     return x[1:65]
  7.    
  8. def foo2(x):
  9.     return x[1:33]
  10.    
  11. def foo3(x):
  12.     return x[1:17]
  13.  
  14. class Example(Module):
  15.     def __init__(self):
  16.    
  17.         d = Signal(128)
  18.         q = Signal(16)
  19.    
  20.         self.comb += q.eq(foo3(foo2(foo1(d))))
  21.  
  22. print(verilog.convert(Example()))
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