exercicio_3

library ieee;
use ieee.std_logic_1164.all;

entity exercicio3 is
port (LEDR: out std_logic_vector(3 downto 0);
		KEY: in std_logic_vector(1 downto 0);
		HEX0: out std_logic_vector(6 downto 0)
		);
end exercicio3;

architecture topo_beh of exercicio3 is
signal Qn: std_logic_vector(3 downto 0);
signal Y: std_logic_vector(3 downto 0);

-----------------componentes------------
component  logica is
port( a: in std_logic_vector(3 downto 0);
		b: out std_logic_vector(3 downto 0)
		);
end component;

component decod7seg is
port (C: in std_logic_vector(3 downto 0);
		F: out std_logic_vector(6 downto 0)
		);
end component;

component D_4FF is --reg
port (CLK: in std_logic;
		RST: in std_logic;
		EN: in std_logic;
		D: in std_logic_vector(3 downto 0);
		Q: out std_logic_vector(3 downto 0)
		);
end component;
----------------------------------------
Begin
	LOG: logica port map( Y(3 downto 0), Qn(3 downto 0) );
	REG: D_4FF port map( KEY(1), KEY(0), '0', Qn(3 downto 0), Y(3 downto 0));
	DEC0: decod7seg port map( Y(3 downto 0), HEX0(6 downto 0) );
end topo_beh;
-- 0 1 3 2 E 6 7 F


------------------------------------------------------- flipflop
library ieee;
use ieee.std_logic_1164.all;
entity D_4FF is
port (
		CLK: in std_logic;
		RST: in std_logic;
		EN: in std_logic;
		D: in std_logic_vector(3 downto 0);
		Q: out std_logic_vector(3 downto 0)
		);
end D_4FF;

architecture behv of D_4FF is
begin
		process(CLK, D, RST, EN)
		begin
			if RST = '0' then
				Q <= "0000";
				elsif (CLK'event and CLK = '1') then
					if EN = '0' then
						Q <= D;
					end if;
			end if;
		end process;
end behv;

-----------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity logica is
port( a: in std_logic_vector(3 downto 0);
		b: out std_logic_vector(3 downto 0)
		);
end logica;

architecture bhv of logica is
begin
	b(3)<= ( not(a(1)) and not(a(0)) )or( a(1) and a(0) and a(2) and not(a(3)) );
	b(2)<= (not(a(3)) and a(0) )or( a(3) and not(a(2)));
	b(1)<= not(a(1)) or not(a(3));
	b(0)<= (not(a(2)) and a(1) )or( a(1) and a(0) and not(a(3)));
end bhv;
---------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;

entity decod7seg is
port (C: in std_logic_vector(3 downto 0);
		F: out std_logic_vector(6 downto 0)
		);
end decod7seg;

architecture decod of decod7seg is
begin
F <= "1000000" when C = "0000" else --0
	  "1111001" when C = "0001" else --1
	  "0000110" when C = "0010" else --2
	  "0000010" when C = "0011" else --3
	  "0011001" when C = "0100" else --4
	  "0110000" when C = "0101" else --5
	  "0100100" when C = "0110" else --6
	  "1111000" when C = "0111" else --7
	  "0000000" when C = "1000" else --8
	  "0011000" when C = "1001" else --9
	  "1111001" when C = "1010" else --A
	  "0000011" when C = "1011" else --B
	  "1000110" when C = "1100" else --C
	  "0100001" when C = "1101" else --D
	  "0000110" when C = "1110" else --E
	  "0001110" when C = "1111" else --F
	  "1111111";
end decod;