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PRU-SWD//ASMx86

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Aug 20th, 2019
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  1. // -*- mode: asm -*-
  2. // pru-swd.p - PRU program to handle SWD protocol
  3. // PRUSS to control SWD signal.
  4.  
  5. .origin 0
  6. entrypoint START
  7.  
  8. #define CONST_DELAY 47 // 470ns To be 1000 kHz
  9.  
  10. //
  11. // DELAY - Macro for do nothing but wait
  12. //
  13. .macro DELAY
  14. JAL r29.w0, DELAY_10NS
  15. .endm
  16.  
  17.  
  18. #define PRU0_ARM_INTERRUPT 19
  19. #define ARM_PRU0_INTERRUPT 21
  20.  
  21. // Constant Table
  22. #define CT_PRUCFG C4
  23. #define CT_PRUDRAM C24
  24.  
  25. // PRU Control register
  26. #define PRU0_CTRL 0x00022000 // address
  27. #define WAKEUP_EN 8 // offset
  28.  
  29. // PRU CFG registers
  30. #define SYSCFG 4 // offset
  31. #define STANDBY_INIT 4 // bit
  32.  
  33. // PRU INTC registers
  34. #define INTC 0x00020000 // address
  35. #define INTC_SICR 0x24 // offset
  36.  
  37. // P8_11 GPIO1_13 GPIO_45 SWD_DIO
  38. // P8_12 GPIO1_12 GPIO_44 SWD_CLK
  39. // P8_15 GPIO1_15 GPIO_47 nRST
  40. #define SWD_DIO_BIT 13
  41. #define SWD_CLK_BIT 12
  42. #define SWD_DIO (1<<SWD_DIO_BIT)
  43. #define SWD_CLK (1<<SWD_CLK_BIT)
  44.  
  45. #define GPIO1_BASE_0100 0x4804c100
  46. // offsets
  47. #define GPIO_OE 0x34
  48. #define GPIO_DATAIN 0x38
  49. #define GPIO_CLEARDATAOUT 0x90
  50. #define GPIO_SETDATAOUT 0x94
  51.  
  52. // LED
  53. // bit 21: USR0, 22: USR1, 23: USR2, 24: USR3
  54.  
  55. // No operation but delay
  56. #define NOP OR r0, r0, r0
  57.  
  58. #define CTBIR_0 0x22020
  59.  
  60. //
  61. // DRIVE_CLK_HIGH - Macro to drive SWD_CLK "High"
  62. //
  63. .macro DRIVE_CLK_HIGH
  64. SBBO r7, r5, GPIO_SETDATAOUT, 4
  65. .endm
  66.  
  67. //
  68. // DRIVE_CLK_LOW - Macro to drive SWD_CLK "Low"
  69. //
  70. .macro DRIVE_CLK_LOW
  71. SBBO r7, r5, GPIO_CLEARDATAOUT, 4
  72. .endm
  73.  
  74. //
  75. // DRIVE_DIO_HIGH - Macro to drive SWD_DIO "High"
  76. //
  77. .macro DRIVE_DIO_HIGH
  78. SBBO r6, r5, GPIO_SETDATAOUT, 4
  79. .endm
  80.  
  81. //
  82. // DRIVE_DIO_LOW - Macro to drive SWD_DIO "Low"
  83. //
  84. .macro DRIVE_DIO_LOW
  85. SBBO r6, r5, GPIO_CLEARDATAOUT, 4
  86. .endm
  87.  
  88. //
  89. // TRN_INPUT - Macro to do TRN-bit for preparing input
  90. //
  91. .macro TRN_INPUT
  92. DRIVE_CLK_LOW
  93. SET_DIO_INPUT r2
  94. DELAY
  95. NOP
  96. DRIVE_CLK_HIGH
  97. DELAY
  98. NOP
  99. NOP
  100. .endm
  101.  
  102. START:
  103. // Enable OCP master port to access GPIO
  104. LBCO r0, CT_PRUCFG, SYSCFG, 4
  105. CLR r0, r0, STANDBY_INIT
  106. SBCO r0, CT_PRUCFG, SYSCFG, 4
  107.  
  108. // Configure C24 to 0x00000000 (PRU0 DRAM)
  109. LDI r0, #0
  110. MOV r1, CTBIR_0
  111. SBBO r0, r1, 0, 4
  112.  
  113. // Registers for constant values
  114. MOV r5, #GPIO1_BASE_0100
  115. LDI r6, #SWD_DIO
  116. LDI r7, #SWD_CLK
  117.  
  118. // Initialize SWD_DIO and SWD_CLK pins
  119. DRIVE_DIO_HIGH
  120. DRIVE_CLK_HIGH
  121. // SWD_DIO_oe <= Output, SWD_CLK_oe <= Output
  122. LBBO r0, r5, GPIO_OE, 4
  123. CLR r0, SWD_DIO_BIT
  124. CLR r0, SWD_CLK_BIT
  125. SBBO r0, r5, GPIO_OE, 4
  126.  
  127. // Wakeup control configuration
  128. MOV r0, #PRU0_CTRL
  129. MOV r1, #0xffffffff
  130. SBBO r1, r0, WAKEUP_EN, 4
  131.  
  132. // Clear the counter
  133. LDI r0, #0
  134. SBCO r0, CT_PRUDRAM, 72, 4
  135.  
  136. QBA COMMAND_LOOP
  137.  
  138. //
  139. // BLINK - Blink LED
  140. //
  141. BLINK:
  142. LBCO r0, CT_PRUDRAM, 4, 12
  143. //
  144. // R0 = delay
  145. // R1 = number of loops
  146. // R2 = LED bit value
  147. //
  148. LOOP0:
  149. SBBO r2, r5, GPIO_SETDATAOUT, 4
  150. MOV r3, r0
  151. LOOP1:
  152. SUB r3, r3, 1
  153. QBNE LOOP1, r3, 0
  154.  
  155. SBBO r2, r5, GPIO_CLEARDATAOUT, 4
  156. MOV r3, r0
  157. LOOP2:
  158. SUB r3, r3, 1
  159. QBNE LOOP2, r3, 0
  160.  
  161. SUB r1, r1, 1
  162. QBNE LOOP0, r1, 0
  163.  
  164. LDI r0, #0
  165. SBCO r0, CT_PRUDRAM, 64, 4
  166. QBA COMMAND_DONE
  167.  
  168.  
  169. //
  170. // GPIO_OUT - Output to GPIO pin
  171. //
  172. GPIO_OUT:
  173. //
  174. // R0 = bit-value
  175. // R1 = value
  176. //
  177. LBCO r0, CT_PRUDRAM, 4, 8
  178. //
  179. QBBS L_GPIO_OUT_1, r1.t0
  180. SBBO r0, r5, GPIO_CLEARDATAOUT, 4
  181. QBA L_GPIO_OUT_DONE
  182. L_GPIO_OUT_1:
  183. SBBO r0, r5, GPIO_SETDATAOUT, 4
  184. NOP
  185. L_GPIO_OUT_DONE:
  186. //
  187. LDI r0, #0
  188. SBCO r0, CT_PRUDRAM, 64, 4
  189. QBA COMMAND_DONE
  190.  
  191.  
  192. //
  193. // GPIO_IN - Input from GPIO pin
  194. //
  195. GPIO_IN:
  196. LBBO r0, r5, GPIO_DATAIN, 4
  197. //
  198. // RETURN: Value
  199. SBCO r0, CT_PRUDRAM, 64, 4
  200. QBA COMMAND_DONE
  201.  
  202.  
  203. //
  204. // SET_DIO_OUTPUT - Macro to set mode of SWD_DIO to output
  205. //
  206. .macro SET_DIO_OUTPUT
  207. .mparam rx
  208. // SWD_DIO_oe <= Output
  209. LBBO rx, r5, GPIO_OE, 4
  210. CLR rx, SWD_DIO_BIT
  211. SBBO rx, r5, GPIO_OE, 4
  212. .endm
  213.  
  214. //
  215. // SET_DIO_INPUT - Macro to set mode of SWD_DIO to input
  216. //
  217. .macro SET_DIO_INPUT
  218. .mparam rx
  219. // SWD_DIO_oe <= Input
  220. LBBO rx, r5, GPIO_OE, 4
  221. SET rx, SWD_DIO_BIT
  222. SBBO rx, r5, GPIO_OE, 4
  223. .endm
  224.  
  225. DO_SIG_IDLE:
  226. L_SIG_IDLE:
  227. DRIVE_CLK_LOW
  228. DELAY
  229. NOP
  230. NOP
  231. DRIVE_CLK_HIGH
  232. DELAY
  233. SUB r0, r0, 1
  234. QBNE L_SIG_IDLE, r0, 0
  235. RET
  236.  
  237. //
  238. // SIG_IDLE - Park SWD_DIO = Low and strobe SWD_CLK
  239. //
  240. SIG_IDLE:
  241. //
  242. // R0 = count
  243. //
  244. LBCO r0, CT_PRUDRAM, 4, 4
  245. //
  246. DRIVE_DIO_LOW
  247. //
  248. JAL r30.w0, DO_SIG_IDLE
  249. //
  250. DRIVE_DIO_HIGH
  251. //
  252. LDI r0, #0
  253. SBCO r0, CT_PRUDRAM, 64, 4
  254. QBA COMMAND_DONE
  255.  
  256. //
  257. // SIG_GEN - Generate signal pattern on SWD_DIO with SWD_CLK strobe
  258. //
  259. SIG_GEN:
  260. //
  261. // R0 = bit-count
  262. //
  263. LDI r0, #0
  264. LBCO r0.b0, CT_PRUDRAM, 1, 1
  265. //
  266. // R16..R23: Bit pattern (256-bit maximum)
  267. //
  268. LBCO r16, CT_PRUDRAM, 4, 32
  269. //
  270. // Start with r16, from LSB
  271. MOV r1.b0, &r16
  272. LDI r2, #1
  273. MVID r3, *r1.b0++
  274. L_GEN_LOOP:
  275. SUB r0, r0, 1
  276. LSL r2, r2, 1
  277. QBBS L_GEN_BIT1, r3.t0
  278. LSR r3, r3, 1
  279. DRIVE_CLK_LOW
  280. DRIVE_DIO_LOW
  281. QBA L_GEN_BIT_DONE
  282. //
  283. L_NO_LOAD:
  284. NOP
  285. QBA L_NEXT_BIT
  286. //
  287. L_GEN_BIT1:
  288. LSR r3, r3, 1
  289. DRIVE_CLK_LOW
  290. DRIVE_DIO_HIGH
  291. NOP
  292. L_GEN_BIT_DONE:
  293. //
  294. DELAY
  295. QBNE L_NO_LOAD, r2, 0
  296. MVID r3, *r1.b0++
  297. LDI r2, #1
  298. L_NEXT_BIT:
  299. DRIVE_CLK_HIGH
  300. DELAY
  301. QBNE L_GEN_LOOP, r0, 0
  302. //
  303. L_SIG_GEN_DONE:
  304. LDI r0, #0
  305. SBCO r0, CT_PRUDRAM, 64, 4
  306. //
  307. DRIVE_DIO_HIGH
  308. QBA COMMAND_DONE
  309.  
  310. ///////////////////////////////////////////////////////////////////////////
  311. COMMAND_DONE:
  312. // Increment the counter
  313. LBCO r0, CT_PRUDRAM, 72, 4
  314. ADD r0, r0, #1
  315. SBCO r0, CT_PRUDRAM, 72, 4
  316.  
  317. // Clear the event
  318. MOV r1, #INTC
  319. LDI r2, #ARM_PRU0_INTERRUPT
  320. SBBO r2, r1, INTC_SICR, 4
  321.  
  322. // Notify Host
  323. MOV r31.b0, PRU0_ARM_INTERRUPT+16
  324.  
  325. COMMAND_LOOP:
  326. // Wait until host wakes up PRU0
  327. SLP 1
  328.  
  329. // Load values from data RAM into register R0
  330. LBCO r0, CT_PRUDRAM, 0, 1
  331.  
  332. QBBS L_1xx, r0.t2
  333. QBBS L_01x, r0.t1
  334. QBBS L_001, r0.t0
  335. L_000: // Command HALT
  336. MOV r0, #0
  337. SBCO r0, CT_PRUDRAM, 64, 4
  338. MOV r31.b0, PRU0_ARM_INTERRUPT+16
  339. HALT
  340. L_001: // Command BLINK
  341. QBA BLINK
  342. L_01x:
  343. QBBS L_011, r0.t0
  344. L_010: // Command GPIO_OUT
  345. QBA GPIO_OUT
  346. L_011: // Command GPIO_IN
  347. QBA GPIO_IN
  348. L_1xx:
  349. QBBS L_11x, r0.t1
  350. QBBS L_101, r0.t0
  351. L_100: // Command SIG_IDLE
  352. QBA SIG_IDLE
  353. L_101: // Command SIG_GEN
  354. QBA SIG_GEN
  355. L_11x:
  356. QBBS L_111, r0.t0
  357. L_110: // Command READ_REG
  358. QBA READ_REG
  359. L_111: // Command WRITE_REG
  360. QBA WRITE_REG
  361. ///////////////////////////////////////////////////////////////////////////
  362.  
  363. DELAY_10NS: // delay_clocks = CONST_DELAY * 2 + 2
  364. LDI r8, #CONST_DELAY
  365. L_DELAY:
  366. SUB r8, r8, 1
  367. QBNE L_DELAY, r8, 1
  368. JMP r29.w0
  369.  
  370. //
  371. // WRITE_SWD_DIO_BIT_NO_LAST_NOP - Macro writing SWD_DIO bit, but NOP
  372. //
  373. .macro WRITE_SWD_DIO_BIT_NO_LAST_NOP
  374. .mparam src_bit, label_bit1, label_done
  375. QBBS label_bit1, src_bit
  376. DRIVE_CLK_LOW
  377. DRIVE_DIO_LOW
  378. QBA label_done
  379. label_bit1:
  380. DRIVE_CLK_LOW
  381. DRIVE_DIO_HIGH
  382. NOP
  383. label_done:
  384. DELAY
  385. DRIVE_CLK_HIGH // <---- Target read
  386. DELAY
  387. .endm
  388. //
  389. // WRITE_SWD_DIO_BIT_NO_LAST_NOP - Macro writing SWD_DIO bit, with NOP
  390. //
  391. .macro WRITE_SWD_DIO_BIT
  392. .mparam src_bit, label_bit1, label_done
  393. WRITE_SWD_DIO_BIT_NO_LAST_NOP src_bit, label_bit1, label_done
  394. NOP
  395. .endm
  396. //
  397. // READ_SWD_DIO_BIT - Macro reading SWD_DIO bit onto register Rx
  398. //
  399. .macro READ_SWD_DIO_BIT
  400. .mparam rx, ry, label_1, label_done, shift=1
  401. DRIVE_CLK_LOW
  402. DELAY
  403. LBBO ry, r5, GPIO_DATAIN, 4
  404. LSR rx, rx, shift
  405. DRIVE_CLK_HIGH
  406. QBBS label_1, ry, SWD_DIO_BIT
  407. QBA label_done
  408. label_1:
  409. SET rx, 31
  410. label_done:
  411. DELAY
  412. .endm
  413. //
  414. // READ_REG - execute READ_REG transaction
  415. //
  416. READ_REG:
  417. //
  418. // R0 = command
  419. //
  420. LDI r0, #0
  421. LBCO r0.b0, CT_PRUDRAM, 1, 1
  422. LBCO r0.b2, CT_PRUDRAM, 3, 1
  423. //
  424. //
  425. //
  426. WRITE_SWD_DIO_BIT r0.t0, L_RRC0_BIT1, L_RRC0_DONE
  427. WRITE_SWD_DIO_BIT r0.t1, L_RRC1_BIT1, L_RRC1_DONE
  428. WRITE_SWD_DIO_BIT r0.t2, L_RRC2_BIT1, L_RRC2_DONE
  429. WRITE_SWD_DIO_BIT r0.t3, L_RRC3_BIT1, L_RRC3_DONE
  430. WRITE_SWD_DIO_BIT r0.t4, L_RRC4_BIT1, L_RRC4_DONE
  431. WRITE_SWD_DIO_BIT r0.t5, L_RRC5_BIT1, L_RRC5_DONE
  432. WRITE_SWD_DIO_BIT r0.t6, L_RRC6_BIT1, L_RRC6_DONE
  433. WRITE_SWD_DIO_BIT r0.t7, L_RRC7_BIT1, L_RRC7_DONE
  434. NOP
  435. //
  436. TRN_INPUT
  437. // Read ACK bits onto R3
  438. READ_SWD_DIO_BIT r3, r2, L_RRD0_1, L_RRD0_F
  439. READ_SWD_DIO_BIT r3, r2, L_RRD1_1, L_RRD1_F
  440. READ_SWD_DIO_BIT r3, r2, L_RRD2_1, L_RRD2_F
  441. // Read RDATA bits onto R4
  442. READ_SWD_DIO_BIT r4, r2, L_RRD3_1, L_RRD3_F
  443. READ_SWD_DIO_BIT r4, r2, L_RRD4_1, L_RRD4_F
  444. READ_SWD_DIO_BIT r4, r2, L_RRD5_1, L_RRD5_F
  445. READ_SWD_DIO_BIT r4, r2, L_RRD6_1, L_RRD6_F
  446. READ_SWD_DIO_BIT r4, r2, L_RRD7_1, L_RRD7_F
  447. READ_SWD_DIO_BIT r4, r2, L_RRD8_1, L_RRD8_F
  448. READ_SWD_DIO_BIT r4, r2, L_RRD9_1, L_RRD9_F
  449. READ_SWD_DIO_BIT r4, r2, L_RRDa_1, L_RRDa_F
  450. //
  451. READ_SWD_DIO_BIT r4, r2, L_RRDb_1, L_RRDb_F
  452. READ_SWD_DIO_BIT r4, r2, L_RRDc_1, L_RRDc_F
  453. READ_SWD_DIO_BIT r4, r2, L_RRDd_1, L_RRDd_F
  454. READ_SWD_DIO_BIT r4, r2, L_RRDe_1, L_RRDe_F
  455. READ_SWD_DIO_BIT r4, r2, L_RRDf_1, L_RRDf_F
  456. READ_SWD_DIO_BIT r4, r2, L_RRDg_1, L_RRDg_F
  457. READ_SWD_DIO_BIT r4, r2, L_RRDh_1, L_RRDh_F
  458. READ_SWD_DIO_BIT r4, r2, L_RRDi_1, L_RRDi_F
  459. //
  460. READ_SWD_DIO_BIT r4, r2, L_RRDj_1, L_RRDj_F
  461. READ_SWD_DIO_BIT r4, r2, L_RRDk_1, L_RRDk_F
  462. READ_SWD_DIO_BIT r4, r2, L_RRDl_1, L_RRDl_F
  463. READ_SWD_DIO_BIT r4, r2, L_RRDm_1, L_RRDm_F
  464. READ_SWD_DIO_BIT r4, r2, L_RRDn_1, L_RRDn_F
  465. READ_SWD_DIO_BIT r4, r2, L_RRDo_1, L_RRDo_F
  466. READ_SWD_DIO_BIT r4, r2, L_RRDp_1, L_RRDp_F
  467. READ_SWD_DIO_BIT r4, r2, L_RRDq_1, L_RRDq_F
  468. //
  469. READ_SWD_DIO_BIT r4, r2, L_RRDr_1, L_RRDr_F
  470. READ_SWD_DIO_BIT r4, r2, L_RRDs_1, L_RRDs_F
  471. READ_SWD_DIO_BIT r4, r2, L_RRDt_1, L_RRDt_F
  472. READ_SWD_DIO_BIT r4, r2, L_RRDu_1, L_RRDu_F
  473. READ_SWD_DIO_BIT r4, r2, L_RRDv_1, L_RRDv_F
  474. READ_SWD_DIO_BIT r4, r2, L_RRDw_1, L_RRDw_F
  475. READ_SWD_DIO_BIT r4, r2, L_RRDx_1, L_RRDx_F
  476. READ_SWD_DIO_BIT r4, r2, L_RRDy_1, L_RRDy_F
  477. // Parity bit
  478. READ_SWD_DIO_BIT r3, r2, L_RRDz_1, L_RRDz_F, 29
  479. // TRN
  480. DRIVE_CLK_LOW
  481. DELAY
  482. NOP
  483. NOP
  484. DRIVE_CLK_HIGH
  485. //
  486. DELAY
  487. LSR r0, r0, 16
  488. QBEQ L_SKIP_IDLE_R, r0, 0
  489. DRIVE_DIO_LOW
  490. SET_DIO_OUTPUT r2
  491. JAL r30.w0, DO_SIG_IDLE
  492. //
  493. L_SKIP_IDLE_R:
  494. DRIVE_DIO_HIGH
  495. SET_DIO_OUTPUT r2
  496. // RETURN: Parity|Ack, Value
  497. SBCO r3, CT_PRUDRAM, 64, 8
  498. QBA COMMAND_DONE
  499.  
  500. //
  501. // WRITE_REG - execute WRITE_REG transaction
  502. //
  503. WRITE_REG:
  504. //
  505. // R0 = command + parity_as_t8
  506. // R1 = value
  507. //
  508. LDI r0, #0
  509. LBCO r0.b0, CT_PRUDRAM, 1, 1
  510. LBCO r0.b1, CT_PRUDRAM, 2, 1
  511. LBCO r0.b2, CT_PRUDRAM, 3, 1
  512. LBCO r1, CT_PRUDRAM, 4, 8
  513. //
  514. //
  515. WRITE_SWD_DIO_BIT r0.t0, L_WRC0_BIT1, L_WRC0_DONE
  516. WRITE_SWD_DIO_BIT r0.t1, L_WRC1_BIT1, L_WRC1_DONE
  517. WRITE_SWD_DIO_BIT r0.t2, L_WRC2_BIT1, L_WRC2_DONE
  518. WRITE_SWD_DIO_BIT r0.t3, L_WRC3_BIT1, L_WRC3_DONE
  519. WRITE_SWD_DIO_BIT r0.t4, L_WRC4_BIT1, L_WRC4_DONE
  520. WRITE_SWD_DIO_BIT r0.t5, L_WRC5_BIT1, L_WRC5_DONE
  521. WRITE_SWD_DIO_BIT r0.t6, L_WRC6_BIT1, L_WRC6_DONE
  522. WRITE_SWD_DIO_BIT r0.t7, L_WRC7_BIT1, L_WRC7_DONE
  523. NOP
  524. //
  525. TRN_INPUT
  526. // Read ACK bits onto R3
  527. READ_SWD_DIO_BIT r3, r2, L_WRA0_1, L_WRA0_F
  528. READ_SWD_DIO_BIT r3, r2, L_WRA1_1, L_WRA1_F
  529. READ_SWD_DIO_BIT r3, r2, L_WRA2_1, L_WRA2_F
  530. //
  531. // TRN and WRITE the first bit
  532. DRIVE_CLK_LOW
  533. DELAY
  534. NOP
  535. QBBS L_WRD0_BIT1, r1.t0
  536. DRIVE_CLK_HIGH
  537. DRIVE_DIO_LOW
  538. QBA L_WRD0_DONE
  539. L_WRD0_BIT1:
  540. DRIVE_CLK_HIGH
  541. DRIVE_DIO_HIGH
  542. NOP
  543. L_WRD0_DONE:
  544. DELAY
  545. DRIVE_CLK_LOW
  546. SET_DIO_OUTPUT r2
  547. DELAY
  548. NOP
  549. DRIVE_CLK_HIGH
  550. DELAY
  551. NOP
  552. //
  553. WRITE_SWD_DIO_BIT r1.t1, L_WRD1_BIT1, L_WRD1_DONE
  554. WRITE_SWD_DIO_BIT r1.t2, L_WRD2_BIT1, L_WRD2_DONE
  555. WRITE_SWD_DIO_BIT r1.t3, L_WRD3_BIT1, L_WRD3_DONE
  556. WRITE_SWD_DIO_BIT r1.t4, L_WRD4_BIT1, L_WRD4_DONE
  557. WRITE_SWD_DIO_BIT r1.t5, L_WRD5_BIT1, L_WRD5_DONE
  558. WRITE_SWD_DIO_BIT r1.t6, L_WRD6_BIT1, L_WRD6_DONE
  559. WRITE_SWD_DIO_BIT r1.t7, L_WRD7_BIT1, L_WRD7_DONE
  560. WRITE_SWD_DIO_BIT r1.t8, L_WRD8_BIT1, L_WRD8_DONE
  561. WRITE_SWD_DIO_BIT r1.t9, L_WRD9_BIT1, L_WRD9_DONE
  562. WRITE_SWD_DIO_BIT r1.t10, L_WRDa_BIT1, L_WRDa_DONE
  563. WRITE_SWD_DIO_BIT r1.t11, L_WRDb_BIT1, L_WRDb_DONE
  564. WRITE_SWD_DIO_BIT r1.t12, L_WRDc_BIT1, L_WRDc_DONE
  565. WRITE_SWD_DIO_BIT r1.t13, L_WRDd_BIT1, L_WRDd_DONE
  566. WRITE_SWD_DIO_BIT r1.t14, L_WRDe_BIT1, L_WRDe_DONE
  567. WRITE_SWD_DIO_BIT r1.t15, L_WRDf_BIT1, L_WRDf_DONE
  568. WRITE_SWD_DIO_BIT r1.t16, L_WRDg_BIT1, L_WRDg_DONE
  569. WRITE_SWD_DIO_BIT r1.t17, L_WRDh_BIT1, L_WRDh_DONE
  570. WRITE_SWD_DIO_BIT r1.t18, L_WRDi_BIT1, L_WRDi_DONE
  571. WRITE_SWD_DIO_BIT r1.t19, L_WRDj_BIT1, L_WRDj_DONE
  572. WRITE_SWD_DIO_BIT r1.t20, L_WRDk_BIT1, L_WRDk_DONE
  573. WRITE_SWD_DIO_BIT r1.t21, L_WRDl_BIT1, L_WRDl_DONE
  574. WRITE_SWD_DIO_BIT r1.t22, L_WRDm_BIT1, L_WRDm_DONE
  575. WRITE_SWD_DIO_BIT r1.t23, L_WRDn_BIT1, L_WRDn_DONE
  576. WRITE_SWD_DIO_BIT r1.t24, L_WRDo_BIT1, L_WRDo_DONE
  577. WRITE_SWD_DIO_BIT r1.t25, L_WRDp_BIT1, L_WRDp_DONE
  578. WRITE_SWD_DIO_BIT r1.t26, L_WRDq_BIT1, L_WRDq_DONE
  579. WRITE_SWD_DIO_BIT r1.t27, L_WRDr_BIT1, L_WRDr_DONE
  580. WRITE_SWD_DIO_BIT r1.t28, L_WRDs_BIT1, L_WRDs_DONE
  581. WRITE_SWD_DIO_BIT r1.t29, L_WRDt_BIT1, L_WRDt_DONE
  582. WRITE_SWD_DIO_BIT r1.t30, L_WRDu_BIT1, L_WRDu_DONE
  583. WRITE_SWD_DIO_BIT r1.t31, L_WRDv_BIT1, L_WRDv_DONE
  584. WRITE_SWD_DIO_BIT_NO_LAST_NOP r0.t8, L_WRDw_BIT1, L_WRDw_DONE
  585. //
  586. LSR r0, r0, 16
  587. QBEQ L_SKIP_IDLE_W, r0, 0
  588. DRIVE_DIO_LOW
  589. JAL r30.w0, DO_SIG_IDLE
  590. //
  591. L_SKIP_IDLE_W:
  592. DRIVE_DIO_HIGH
  593. // RETURN: Ack
  594. LSR r3, r3, 29
  595. SBCO r3, CT_PRUDRAM, 64, 4
  596. JMP COMMAND_DONE
  597. //
  598. // Local Variables:
  599. // compile-command: "pasm -V3 -l -b pru-swd.p"
  600. // End:
  601. //
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