Create a new version of paste:

root@pinebook:~# 7z b

7-Zip 9.20  Copyright (c) 1999-2010 Igor Pavlov  2010-11-18
p7zip Version 9.20 (locale=en_US.UTF-8,Utf16=on,HugeFiles=on,4 CPUs)

RAM size:    1989 MB,  # CPU hardware threads:   4
RAM usage:    850 MB,  # Benchmark threads:      4

Dict        Compressing          |        Decompressing
      Speed Usage    R/U Rating  |    Speed Usage    R/U Rating
       KB/s     %   MIPS   MIPS  |     KB/s     %   MIPS   MIPS

22:    1363   290    456   1326  |    40210   389    933   3627
23:    1312   290    461   1336  |    38584   380    929   3530
24:    1305   299    469   1404  |    38616   387    926   3582
25:    1265   304    475   1445  |    37719   386    918   3547
----------------------------------------------------------------
Avr:          296    465   1378               385    926   3572
Tot:          341    696   2475

root@pinebook:~/tinymembench# ./tinymembench 
tinymembench v0.4.9 (simple benchmark for memory throughput and latency)

==========================================================================
== Memory bandwidth tests                                               ==
==                                                                      ==
== Note 1: 1MB = 1000000 bytes                                          ==
== Note 2: Results for 'copy' tests show how many bytes can be          ==
==         copied per second (adding together read and writen           ==
==         bytes would have provided twice higher numbers)              ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
==         to first fetch data into it, and only then write it to the   ==
==         destination (source -> L1 cache, L1 cache -> destination)    ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in    ==
==         brackets                                                     ==
==========================================================================

 C copy backwards                                     :    971.2 MB/s (3.6%)
 C copy backwards (32 byte blocks)                    :    973.5 MB/s (2.1%)
 C copy backwards (64 byte blocks)                    :    973.5 MB/s (2.8%)
 C copy                                               :    974.6 MB/s (2.5%)
 C copy prefetched (32 bytes step)                    :    769.2 MB/s (2.0%)
 C copy prefetched (64 bytes step)                    :    894.2 MB/s (1.8%)
 C 2-pass copy                                        :    934.8 MB/s
 C 2-pass copy prefetched (32 bytes step)             :    692.0 MB/s (2.0%)
 C 2-pass copy prefetched (64 bytes step)             :    469.0 MB/s (3.5%)
 C fill                                               :   3092.4 MB/s (1.2%)
 C fill (shuffle within 16 byte blocks)               :   3093.2 MB/s (1.3%)
 C fill (shuffle within 32 byte blocks)               :   3092.7 MB/s
 C fill (shuffle within 64 byte blocks)               :   3090.2 MB/s (3.7%)
 ---
 standard memcpy                                      :    887.4 MB/s (2.8%)
 standard memset                                      :   3087.6 MB/s (4.3%)
 ---
 NEON LDP/STP copy                                    :    991.9 MB/s (1.9%)
 NEON LDP/STP copy pldl2strm (32 bytes step)          :    720.8 MB/s (1.5%)
 NEON LDP/STP copy pldl2strm (64 bytes step)          :    883.1 MB/s
 NEON LDP/STP copy pldl1keep (32 bytes step)          :   1036.8 MB/s (2.3%)
 NEON LDP/STP copy pldl1keep (64 bytes step)          :   1035.9 MB/s (1.4%)
 NEON LD1/ST1 copy                                    :    994.8 MB/s (1.1%)
 NEON STP fill                                        :   3094.3 MB/s (0.9%)
 NEON STNP fill                                       :   2138.6 MB/s (11.3%)
 ARM LDP/STP copy                                     :    994.5 MB/s (2.0%)
 ARM STP fill                                         :   3095.2 MB/s (1.0%)
 ARM STNP fill                                        :   2182.0 MB/s (6.5%)

==========================================================================
== Framebuffer read tests.                                              ==
==                                                                      ==
== Many ARM devices use a part of the system memory as the framebuffer, ==
== typically mapped as uncached but with write-combining enabled.       ==
== Writes to such framebuffers are quite fast, but reads are much       ==
== slower and very sensitive to the alignment and the selection of      ==
== CPU instructions which are used for accessing memory.                ==
==                                                                      ==
== Many x86 systems allocate the framebuffer in the GPU memory,         ==
== accessible for the CPU via a relatively slow PCI-E bus. Moreover,    ==
== PCI-E is asymmetric and handles reads a lot worse than writes.       ==
==                                                                      ==
== If uncached framebuffer reads are reasonably fast (at least 100 MB/s ==
== or preferably >300 MB/s), then using the shadow framebuffer layer    ==
== is not necessary in Xorg DDX drivers, resulting in a nice overall    ==
== performance improvement. For example, the xf86-video-fbturbo DDX     ==
== uses this trick.                                                     ==
==========================================================================

 NEON LDP/STP copy (from framebuffer)                 :    148.4 MB/s
 NEON LDP/STP 2-pass copy (from framebuffer)          :    142.2 MB/s (0.4%)
 NEON LD1/ST1 copy (from framebuffer)                 :     37.8 MB/s
 NEON LD1/ST1 2-pass copy (from framebuffer)          :     37.4 MB/s (0.3%)
 ARM LDP/STP copy (from framebuffer)                  :     75.2 MB/s (0.5%)
 ARM LDP/STP 2-pass copy (from framebuffer)           :     73.5 MB/s (0.4%)

==========================================================================
== Memory latency test                                                  ==
==                                                                      ==
== Average time is measured for random memory accesses in the buffers   ==
== of different sizes. The larger is the buffer, the more significant   ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM      ==
== accesses. For extremely large buffer sizes we are expecting to see   ==
== page table walk with several requests to SDRAM for almost every      ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest).                                         ==
==                                                                      ==
== Note 1: All the numbers are representing extra time, which needs to  ==
==         be added to L1 cache latency. The cycle timings for L1 cache ==
==         latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
==         two independent memory accesses at a time. In the case if    ==
==         the memory subsystem can't handle multiple outstanding       ==
==         requests, dual random read has the same timings as two       ==
==         single reads performed one after another.                    ==
==========================================================================

block size : single random read / dual random read
      1024 :    0.0 ns          /     0.0 ns 
      2048 :    0.0 ns          /     0.0 ns 
      4096 :    0.0 ns          /     0.0 ns 
      8192 :    0.0 ns          /     0.0 ns 
     16384 :    0.0 ns          /     0.0 ns 
     32768 :    0.0 ns          /     0.0 ns 
     65536 :    5.9 ns          /    10.0 ns 
    131072 :    9.1 ns          /    13.9 ns 
    262144 :   10.7 ns          /    15.5 ns 
    524288 :   13.0 ns          /    18.1 ns 
   1048576 :  111.9 ns          /   174.1 ns 
   2097152 :  162.3 ns          /   225.3 ns 
   4194304 :  196.0 ns          /   250.0 ns 
   8388608 :  215.2 ns          /   259.8 ns 
  16777216 :  227.1 ns          /   264.8 ns 
  33554432 :  234.0 ns          /   268.1 ns 
  67108864 :  238.6 ns          /   270.3 ns