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[ember@FreeBSD ~]$ pcm.x 1 Intel(r) Performance Counter Monitor V2.8 (2014-12-18 12:52:39 +0100 ID=ba39a89) Copyright (c) 2009-2014 Intel Corporation Number of physical cores: 1 Number of logical cores: 8 Number of online logical cores: 8 Threads (logical cores) per physical core: 8 Num sockets: 1 Physical cores per socket: 1 Core PMU (perfmon) version: 3 Number of core PMU generic (programmable) counters: 4 Width of generic (programmable) counters: 48 bits Number of core PMU fixed counters: 3 Width of fixed counters: 48 bits Can not access CPUs Model Specific Registers (MSRs). Ensure cpuctl module is loaded and that you have read and write permissions for /dev/cpuctl* devices (the 'chown' command can help). Delay: 1 Access to Intel(r) Performance Counter Monitor has denied (no MSR or PCI CFG space access). [ember@FreeBSD ~]$ sudo pcm.x 1 Intel(r) Performance Counter Monitor V2.8 (2014-12-18 12:52:39 +0100 ID=ba39a89) Copyright (c) 2009-2014 Intel Corporation Number of physical cores: 4 Number of logical cores: 8 Number of online logical cores: 8 Threads (logical cores) per physical core: 2 Num sockets: 1 Physical cores per socket: 4 Core PMU (perfmon) version: 3 Number of core PMU generic (programmable) counters: 4 Width of generic (programmable) counters: 48 bits Number of core PMU fixed counters: 3 Width of fixed counters: 48 bits Nominal core frequency: 2200000000 Hz Package thermal spec power: 35 Watt; Package minimum power: 24 Watt; Package maximum power: 0 Watt; Delay: 1 Detected Intel(R) Core(TM) i7-3632QM CPU @ 2.20GHz "Intel(r) microarchitecture codename Ivy Bridge" EXEC : instructions per nominal CPU cycle IPC : instructions per CPU cycle FREQ : relation to nominal CPU frequency='unhalted clock ticks'/'invariant timer ticks' (includes Intel Turbo Boost) AFREQ : relation to nominal CPU frequency while in active state (not in power-saving C state)='unhalted clock ticks'/'invariant timer ticks while in C0-state' (includes Intel Turbo Boost) L3MISS: L3 cache misses L2MISS: L2 cache misses (including other core's L2 cache *hits*) L3HIT : L3 cache hit ratio (0.00-1.00) L2HIT : L2 cache hit ratio (0.00-1.00) L3CLK : ratio of CPU cycles lost due to L3 cache misses (0.00-1.00), in some cases could be >1.0 due to a higher memory latency L2CLK : ratio of CPU cycles lost due to missing L2 cache but still hitting L3 cache (0.00-1.00) READ : bytes read from memory controller (in GBytes) WRITE : bytes written to memory controller (in GBytes) IO : bytes read/written due to IO requests to memory controller (in GBytes); this may be an over estimate due to same-cache-line partial requests TEMP : Temperature reading in 1 degree Celsius relative to the TjMax temperature (thermal headroom): 0 corresponds to the max temperature Core (SKT) | EXEC | IPC | FREQ | AFREQ | L3MISS | L2MISS | L3HIT | L2HIT | L3CLK | L2CLK | READ | WRITE | IO | TEMP | 0 0 0.00 0.23 0.00 0.55 20 K 22 K 0.06 0.01 1.03 0.01 N/A N/A N/A 75 1 0 0.00 0.24 0.00 0.55 8552 9044 0.05 0.01 1.42 0.02 N/A N/A N/A 75 2 0 0.00 0.47 0.00 0.55 7583 8003 0.05 0.00 1.08 0.02 N/A N/A N/A 75 3 0 0.00 0.23 0.00 0.55 6082 6370 0.05 0.00 1.42 0.02 N/A N/A N/A 75 4 0 0.00 0.21 0.00 0.55 51 K 57 K 0.10 0.00 1.40 0.03 N/A N/A N/A 75 5 0 0.00 0.19 0.00 0.55 6777 6950 0.02 0.00 1.60 0.01 N/A N/A N/A 75 6 0 0.00 0.35 0.00 0.55 24 K 26 K 0.09 0.00 1.00 0.02 N/A N/A N/A 75 7 0 0.00 0.29 0.00 0.55 5230 5365 0.03 0.03 1.39 0.01 N/A N/A N/A 75 ----------------------------------------------------------------------------------------------------------------------------- SKT 0 0.00 0.27 0.00 0.55 130 K 141 K 0.08 0.00 1.23 0.02 0.37 0.00 0.36 74 ----------------------------------------------------------------------------------------------------------------------------- TOTAL * 0.00 0.27 0.00 0.55 130 K 141 K 0.08 0.00 1.23 0.02 0.37 0.00 0.36 N/A Instructions retired: 5108 K ; Active cycles: 19 M ; Time (TSC): 2335 Mticks ; C0 (active,non-halted) core residency: 0.19 % C1 core residency: 0.24 %; C3 core residency: 0.23 %; C6 core residency: 0.00 %; C7 core residency: 99.34 %; C2 package residency: 1.26 %; C3 package residency: 0.22 %; C6 package residency: 0.62 %; C7 package residency: 96.38 %; PHYSICAL CORE IPC : 0.53 => corresponds to 13.29 % utilization for cores in active state Instructions per nominal CPU cycle: 0.00 => corresponds to 0.01 % core utilization over time interval ---------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------- SKT 0 package consumed 3.34 Joules ---------------------------------------------------------------------------------------------- TOTAL: 3.34 Joules EXEC : instructions per nominal CPU cycle IPC : instructions per CPU cycle FREQ : relation to nominal CPU frequency='unhalted clock ticks'/'invariant timer ticks' (includes Intel Turbo Boost) AFREQ : relation to nominal CPU frequency while in active state (not in power-saving C state)='unhalted clock ticks'/'invariant timer ticks while in C0-state' (includes Intel Turbo Boost) L3MISS: L3 cache misses L2MISS: L2 cache misses (including other core's L2 cache *hits*) L3HIT : L3 cache hit ratio (0.00-1.00) L2HIT : L2 cache hit ratio (0.00-1.00) L3CLK : ratio of CPU cycles lost due to L3 cache misses (0.00-1.00), in some cases could be >1.0 due to a higher memory latency L2CLK : ratio of CPU cycles lost due to missing L2 cache but still hitting L3 cache (0.00-1.00) READ : bytes read from memory controller (in GBytes) WRITE : bytes written to memory controller (in GBytes) IO : bytes read/written due to IO requests to memory controller (in GBytes); this may be an over estimate due to same-cache-line partial requests TEMP : Temperature reading in 1 degree Celsius relative to the TjMax temperature (thermal headroom): 0 corresponds to the max temperature Core (SKT) | EXEC | IPC | FREQ | AFREQ | L3MISS | L2MISS | L3HIT | L2HIT | L3CLK | L2CLK | READ | WRITE | IO | TEMP | 0 0 0.00 0.25 0.00 0.55 27 K 29 K 0.07 0.03 1.11 0.02 N/A N/A N/A 76 1 0 0.00 0.24 0.00 0.55 4943 6357 0.22 0.01 0.92 0.06 N/A N/A N/A 76 2 0 0.00 0.39 0.00 0.55 7678 7980 0.04 0.00 1.19 0.01 N/A N/A N/A 76 3 0 0.00 0.23 0.00 0.55 8499 10 K 0.16 0.00 1.00 0.05 N/A N/A N/A 76 4 0 0.00 0.21 0.00 0.55 48 K 55 K 0.12 0.00 1.28 0.03 N/A N/A N/A 76 5 0 0.00 0.31 0.00 0.55 12 K 13 K 0.05 0.07 1.21 0.01 N/A N/A N/A 76 6 0 0.00 0.35 0.00 0.55 23 K 25 K 0.08 0.00 1.04 0.02 N/A N/A N/A 76 7 0 0.00 0.51 0.00 0.55 9961 10 K 0.05 0.03 0.88 0.01 N/A N/A N/A 76 ----------------------------------------------------------------------------------------------------------------------------- SKT 0 0.00 0.29 0.00 0.55 142 K 157 K 0.10 0.01 1.12 0.03 0.37 0.00 0.36 75 ----------------------------------------------------------------------------------------------------------------------------- TOTAL * 0.00 0.29 0.00 0.55 142 K 157 K 0.10 0.01 1.12 0.03 0.37 0.00 0.36 N/A Instructions retired: 6595 K ; Active cycles: 22 M ; Time (TSC): 2335 Mticks ; C0 (active,non-halted) core residency: 0.22 % C1 core residency: 0.30 %; C3 core residency: 0.36 %; C6 core residency: 0.00 %; C7 core residency: 99.12 %; C2 package residency: 1.34 %; C3 package residency: 0.35 %; C6 package residency: 0.54 %; C7 package residency: 96.06 %; PHYSICAL CORE IPC : 0.58 => corresponds to 14.45 % utilization for cores in active state Instructions per nominal CPU cycle: 0.00 => corresponds to 0.02 % core utilization over time interval ---------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------- SKT 0 package consumed 3.35 Joules ---------------------------------------------------------------------------------------------- TOTAL: 3.35 Joules EXEC : instructions per nominal CPU cycle IPC : instructions per CPU cycle FREQ : relation to nominal CPU frequency='unhalted clock ticks'/'invariant timer ticks' (includes Intel Turbo Boost) AFREQ : relation to nominal CPU frequency while in active state (not in power-saving C state)='unhalted clock ticks'/'invariant timer ticks while in C0-state' (includes Intel Turbo Boost) L3MISS: L3 cache misses L2MISS: L2 cache misses (including other core's L2 cache *hits*) L3HIT : L3 cache hit ratio (0.00-1.00) L2HIT : L2 cache hit ratio (0.00-1.00) L3CLK : ratio of CPU cycles lost due to L3 cache misses (0.00-1.00), in some cases could be >1.0 due to a higher memory latency L2CLK : ratio of CPU cycles lost due to missing L2 cache but still hitting L3 cache (0.00-1.00) READ : bytes read from memory controller (in GBytes) WRITE : bytes written to memory controller (in GBytes) IO : bytes read/written due to IO requests to memory controller (in GBytes); this may be an over estimate due to same-cache-line partial requests TEMP : Temperature reading in 1 degree Celsius relative to the TjMax temperature (thermal headroom): 0 corresponds to the max temperature Core (SKT) | EXEC | IPC | FREQ | AFREQ | L3MISS | L2MISS | L3HIT | L2HIT | L3CLK | L2CLK | READ | WRITE | IO | TEMP | 0 0 0.00 0.23 0.00 0.55 24 K 25 K 0.06 0.01 1.04 0.01 N/A N/A N/A 70 1 0 0.00 0.23 0.00 0.55 7488 7778 0.04 0.01 1.45 0.02 N/A N/A N/A 70 2 0 0.00 0.48 0.00 0.55 7043 7290 0.03 0.00 1.03 0.01 N/A N/A N/A 70 3 0 0.00 0.22 0.00 0.55 6712 7011 0.04 0.00 1.39 0.01 N/A N/A N/A 70 4 0 0.00 0.21 0.00 0.55 47 K 53 K 0.11 0.00 1.37 0.03 N/A N/A N/A 70 5 0 0.00 0.30 0.00 0.55 12 K 13 K 0.03 0.07 1.30 0.01 N/A N/A N/A 70 6 0 0.00 0.34 0.00 0.55 24 K 26 K 0.09 0.00 0.99 0.02 N/A N/A N/A 70 7 0 0.00 0.51 0.00 0.55 11 K 11 K 0.02 0.03 1.13 0.00 N/A N/A N/A 70 ----------------------------------------------------------------------------------------------------------------------------- SKT 0 0.00 0.29 0.00 0.55 141 K 152 K 0.07 0.01 1.19 0.02 0.37 0.00 0.36 70 ----------------------------------------------------------------------------------------------------------------------------- TOTAL * 0.00 0.29 0.00 0.55 141 K 152 K 0.07 0.01 1.19 0.02 0.37 0.00 0.36 N/A Instructions retired: 6239 K ; Active cycles: 21 M ; Time (TSC): 2330 Mticks ; C0 (active,non-halted) core residency: 0.21 % C1 core residency: 0.26 %; C3 core residency: 0.00 %; C6 core residency: 0.00 %; C7 core residency: 99.53 %; C2 package residency: 1.04 %; C3 package residency: 0.00 %; C6 package residency: 0.61 %; C7 package residency: 96.72 %; PHYSICAL CORE IPC : 0.58 => corresponds to 14.51 % utilization for cores in active state Instructions per nominal CPU cycle: 0.00 => corresponds to 0.02 % core utilization over time interval ---------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------- SKT 0 package consumed 3.33 Joules ---------------------------------------------------------------------------------------------- TOTAL: 3.33 Joules EXEC : instructions per nominal CPU cycle IPC : instructions per CPU cycle FREQ : relation to nominal CPU frequency='unhalted clock ticks'/'invariant timer ticks' (includes Intel Turbo Boost) AFREQ : relation to nominal CPU frequency while in active state (not in power-saving C state)='unhalted clock ticks'/'invariant timer ticks while in C0-state' (includes Intel Turbo Boost) L3MISS: L3 cache misses L2MISS: L2 cache misses (including other core's L2 cache *hits*) L3HIT : L3 cache hit ratio (0.00-1.00) L2HIT : L2 cache hit ratio (0.00-1.00) L3CLK : ratio of CPU cycles lost due to L3 cache misses (0.00-1.00), in some cases could be >1.0 due to a higher memory latency L2CLK : ratio of CPU cycles lost due to missing L2 cache but still hitting L3 cache (0.00-1.00) READ : bytes read from memory controller (in GBytes) WRITE : bytes written to memory controller (in GBytes) IO : bytes read/written due to IO requests to memory controller (in GBytes); this may be an over estimate due to same-cache-line partial requests TEMP : Temperature reading in 1 degree Celsius relative to the TjMax temperature (thermal headroom): 0 corresponds to the max temperature Core (SKT) | EXEC | IPC | FREQ | AFREQ | L3MISS | L2MISS | L3HIT | L2HIT | L3CLK | L2CLK | READ | WRITE | IO | TEMP | 0 0 0.00 0.36 0.00 0.55 33 K 35 K 0.07 0.20 1.02 0.02 N/A N/A N/A 75 1 0 0.00 0.29 0.00 0.55 10 K 11 K 0.11 0.01 1.32 0.04 N/A N/A N/A 75 2 0 0.00 0.51 0.00 0.55 6588 6874 0.04 0.00 1.02 0.01 N/A N/A N/A 75 3 0 0.00 0.38 0.00 0.55 12 K 13 K 0.06 0.07 1.68 0.02 N/A N/A N/A 75 4 0 0.00 0.23 0.00 0.55 46 K 52 K 0.11 0.00 1.16 0.03 N/A N/A N/A 75 5 0 0.00 0.31 0.00 0.55 13 K 14 K 0.02 0.07 1.41 0.01 N/A N/A N/A 75 6 0 0.00 0.34 0.00 0.55 24 K 26 K 0.08 0.00 0.99 0.02 N/A N/A N/A 75 7 0 0.00 0.57 0.00 0.55 18 K 19 K 0.02 0.18 1.14 0.00 N/A N/A N/A 75 ----------------------------------------------------------------------------------------------------------------------------- SKT 0 0.00 0.34 0.00 0.55 166 K 179 K 0.07 0.08 1.14 0.02 0.38 0.00 0.36 74 ----------------------------------------------------------------------------------------------------------------------------- TOTAL * 0.00 0.34 0.00 0.55 166 K 179 K 0.07 0.08 1.14 0.02 0.38 0.00 0.36 N/A Instructions retired: 8995 K ; Active cycles: 26 M ; Time (TSC): 2335 Mticks ; C0 (active,non-halted) core residency: 0.26 % C1 core residency: 0.32 %; C3 core residency: 0.00 %; C6 core residency: 0.00 %; C7 core residency: 99.43 %; C2 package residency: 1.09 %; C3 package residency: 0.00 %; C6 package residency: 0.60 %; C7 package residency: 96.31 %; PHYSICAL CORE IPC : 0.69 => corresponds to 17.18 % utilization for cores in active state Instructions per nominal CPU cycle: 0.00 => corresponds to 0.02 % core utilization over time interval ---------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------- SKT 0 package consumed 3.35 Joules ---------------------------------------------------------------------------------------------- TOTAL: 3.35 Joules EXEC : instructions per nominal CPU cycle IPC : instructions per CPU cycle FREQ : relation to nominal CPU frequency='unhalted clock ticks'/'invariant timer ticks' (includes Intel Turbo Boost) AFREQ : relation to nominal CPU frequency while in active state (not in power-saving C state)='unhalted clock ticks'/'invariant timer ticks while in C0-state' (includes Intel Turbo Boost) L3MISS: L3 cache misses L2MISS: L2 cache misses (including other core's L2 cache *hits*) L3HIT : L3 cache hit ratio (0.00-1.00) L2HIT : L2 cache hit ratio (0.00-1.00) L3CLK : ratio of CPU cycles lost due to L3 cache misses (0.00-1.00), in some cases could be >1.0 due to a higher memory latency L2CLK : ratio of CPU cycles lost due to missing L2 cache but still hitting L3 cache (0.00-1.00) READ : bytes read from memory controller (in GBytes) WRITE : bytes written to memory controller (in GBytes) IO : bytes read/written due to IO requests to memory controller (in GBytes); this may be an over estimate due to same-cache-line partial requests TEMP : Temperature reading in 1 degree Celsius relative to the TjMax temperature (thermal headroom): 0 corresponds to the max temperature Core (SKT) | EXEC | IPC | FREQ | AFREQ | L3MISS | L2MISS | L3HIT | L2HIT | L3CLK | L2CLK | READ | WRITE | IO | TEMP | 0 0 0.00 0.23 0.00 0.55 26 K 30 K 0.11 0.01 1.27 0.03 N/A N/A N/A 75 1 0 0.00 0.22 0.00 0.55 7048 7287 0.03 0.00 1.52 0.01 N/A N/A N/A 75 2 0 0.00 0.28 0.00 0.55 8310 9155 0.09 0.02 0.70 0.01 N/A N/A N/A 75 3 0 0.00 0.38 0.00 0.55 7410 7911 0.06 0.00 1.26 0.02 N/A N/A N/A 75 4 0 0.00 0.23 0.00 0.55 48 K 54 K 0.10 0.00 1.36 0.03 N/A N/A N/A 75 5 0 0.00 0.32 0.00 0.55 13 K 14 K 0.02 0.08 0.90 0.01 N/A N/A N/A 75 6 0 0.00 0.33 0.00 0.55 18 K 20 K 0.09 0.00 0.99 0.02 N/A N/A N/A 75 7 0 0.00 0.50 0.00 0.55 17 K 18 K 0.02 0.06 1.32 0.01 N/A N/A N/A 75 ----------------------------------------------------------------------------------------------------------------------------- SKT 0 0.00 0.29 0.00 0.55 148 K 161 K 0.08 0.02 1.17 0.02 0.37 0.00 0.36 75 ----------------------------------------------------------------------------------------------------------------------------- TOTAL * 0.00 0.29 0.00 0.55 148 K 161 K 0.08 0.02 1.17 0.02 0.37 0.00 0.36 N/A Instructions retired: 6764 K ; Active cycles: 22 M ; Time (TSC): 2335 Mticks ; C0 (active,non-halted) core residency: 0.23 % C1 core residency: 0.28 %; C3 core residency: 0.00 %; C6 core residency: 0.00 %; C7 core residency: 99.49 %; C2 package residency: 1.05 %; C3 package residency: 0.00 %; C6 package residency: 0.53 %; C7 package residency: 96.67 %; PHYSICAL CORE IPC : 0.59 => corresponds to 14.74 % utilization for cores in active state Instructions per nominal CPU cycle: 0.00 => corresponds to 0.02 % core utilization over time interval ---------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------- SKT 0 package consumed 3.34 Joules ---------------------------------------------------------------------------------------------- TOTAL: 3.34 Joules EXEC : instructions per nominal CPU cycle IPC : instructions per CPU cycle FREQ : relation to nominal CPU frequency='unhalted clock ticks'/'invariant timer ticks' (includes Intel Turbo Boost) AFREQ : relation to nominal CPU frequency while in active state (not in power-saving C state)='unhalted clock ticks'/'invariant timer ticks while in C0-state' (includes Intel Turbo Boost) L3MISS: L3 cache misses L2MISS: L2 cache misses (including other core's L2 cache *hits*) L3HIT : L3 cache hit ratio (0.00-1.00) L2HIT : L2 cache hit ratio (0.00-1.00) L3CLK : ratio of CPU cycles lost due to L3 cache misses (0.00-1.00), in some cases could be >1.0 due to a higher memory latency L2CLK : ratio of CPU cycles lost due to missing L2 cache but still hitting L3 cache (0.00-1.00) READ : bytes read from memory controller (in GBytes) WRITE : bytes written to memory controller (in GBytes) IO : bytes read/written due to IO requests to memory controller (in GBytes); this may be an over estimate due to same-cache-line partial requests TEMP : Temperature reading in 1 degree Celsius relative to the TjMax temperature (thermal headroom): 0 corresponds to the max temperature Core (SKT) | EXEC | IPC | FREQ | AFREQ | L3MISS | L2MISS | L3HIT | L2HIT | L3CLK | L2CLK | READ | WRITE | IO | TEMP | 0 0 0.00 0.29 0.00 0.55 45 K 57 K 0.21 0.01 0.96 0.06 N/A N/A N/A 72 1 0 0.00 0.23 0.00 0.55 7925 8225 0.04 0.01 1.63 0.01 N/A N/A N/A 72 2 0 0.00 0.33 0.00 0.55 5853 6971 0.16 0.00 0.76 0.03 N/A N/A N/A 69 3 0 0.00 0.22 0.00 0.55 8456 9438 0.10 0.00 1.21 0.03 N/A N/A N/A 69 4 0 0.00 0.22 0.00 0.55 46 K 53 K 0.13 0.00 1.24 0.04 N/A N/A N/A 69 5 0 0.00 0.31 0.00 0.55 12 K 12 K 0.05 0.08 1.17 0.01 N/A N/A N/A 69 6 0 0.00 0.27 0.00 0.55 3968 4161 0.05 0.00 0.86 0.01 N/A N/A N/A 68 7 0 0.00 0.55 0.00 0.55 8275 8631 0.04 0.03 0.86 0.01 N/A N/A N/A 68 ----------------------------------------------------------------------------------------------------------------------------- SKT 0 0.00 0.28 0.00 0.55 138 K 160 K 0.14 0.01 1.08 0.04 0.37 0.00 0.36 68 ----------------------------------------------------------------------------------------------------------------------------- TOTAL * 0.00 0.28 0.00 0.55 138 K 160 K 0.14 0.01 1.08 0.04 0.37 0.00 0.36 N/A Instructions retired: 6593 K ; Active cycles: 23 M ; Time (TSC): 2335 Mticks ; C0 (active,non-halted) core residency: 0.23 % C1 core residency: 0.30 %; C3 core residency: 0.49 %; C6 core residency: 0.00 %; C7 core residency: 98.99 %; C2 package residency: 1.35 %; C3 package residency: 0.34 %; C6 package residency: 0.50 %; C7 package residency: 96.13 %; PHYSICAL CORE IPC : 0.57 => corresponds to 14.22 % utilization for cores in active state Instructions per nominal CPU cycle: 0.00 => corresponds to 0.02 % core utilization over time interval ---------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------- SKT 0 package consumed 3.35 Joules ---------------------------------------------------------------------------------------------- TOTAL: 3.35 Joules EXEC : instructions per nominal CPU cycle IPC : instructions per CPU cycle FREQ : relation to nominal CPU frequency='unhalted clock ticks'/'invariant timer ticks' (includes Intel Turbo Boost) AFREQ : relation to nominal CPU frequency while in active state (not in power-saving C state)='unhalted clock ticks'/'invariant timer ticks while in C0-state' (includes Intel Turbo Boost) L3MISS: L3 cache misses L2MISS: L2 cache misses (including other core's L2 cache *hits*) L3HIT : L3 cache hit ratio (0.00-1.00) L2HIT : L2 cache hit ratio (0.00-1.00) L3CLK : ratio of CPU cycles lost due to L3 cache misses (0.00-1.00), in some cases could be >1.0 due to a higher memory latency L2CLK : ratio of CPU cycles lost due to missing L2 cache but still hitting L3 cache (0.00-1.00) READ : bytes read from memory controller (in GBytes) WRITE : bytes written to memory controller (in GBytes) IO : bytes read/written due to IO requests to memory controller (in GBytes); this may be an over estimate due to same-cache-line partial requests TEMP : Temperature reading in 1 degree Celsius relative to the TjMax temperature (thermal headroom): 0 corresponds to the max temperature Core (SKT) | EXEC | IPC | FREQ | AFREQ | L3MISS | L2MISS | L3HIT | L2HIT | L3CLK | L2CLK | READ | WRITE | IO | TEMP | 0 0 0.00 0.25 0.00 0.55 24 K 27 K 0.11 0.01 0.97 0.03 N/A N/A N/A 70 1 0 0.00 0.24 0.00 0.55 7466 7726 0.03 0.00 1.37 0.01 N/A N/A N/A 70 2 0 0.00 0.47 0.00 0.55 7482 7835 0.05 0.00 1.05 0.01 N/A N/A N/A 70 3 0 0.00 0.22 0.00 0.55 6732 6957 0.03 0.00 1.43 0.01 N/A N/A N/A 70 4 0 0.00 0.21 0.00 0.55 45 K 51 K 0.12 0.00 1.33 0.03 N/A N/A N/A 70 5 0 0.00 0.33 0.00 0.55 10 K 11 K 0.03 0.09 1.27 0.01 N/A N/A N/A 70 6 0 0.00 0.33 0.00 0.55 20 K 22 K 0.09 0.00 0.95 0.02 N/A N/A N/A 70 7 0 0.00 0.49 0.00 0.55 12 K 13 K 0.01 0.03 1.17 0.00 N/A N/A N/A 70 ----------------------------------------------------------------------------------------------------------------------------- SKT 0 0.00 0.29 0.00 0.55 135 K 148 K 0.08 0.01 1.15 0.02 0.37 0.00 0.36 70 ----------------------------------------------------------------------------------------------------------------------------- TOTAL * 0.00 0.29 0.00 0.55 135 K 148 K 0.08 0.01 1.15 0.02 0.37 0.00 0.36 N/A Instructions retired: 6227 K ; Active cycles: 21 M ; Time (TSC): 2335 Mticks ; C0 (active,non-halted) core residency: 0.21 % C1 core residency: 0.26 %; C3 core residency: 0.00 %; C6 core residency: 0.00 %; C7 core residency: 99.53 %; C2 package residency: 1.14 %; C3 package residency: 0.00 %; C6 package residency: 0.61 %; C7 package residency: 96.62 %; PHYSICAL CORE IPC : 0.59 => corresponds to 14.66 % utilization for cores in active state Instructions per nominal CPU cycle: 0.00 => corresponds to 0.02 % core utilization over time interval ---------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------- SKT 0 package consumed 3.34 Joules ---------------------------------------------------------------------------------------------- TOTAL: 3.34 Joules EXEC : instructions per nominal CPU cycle IPC : instructions per CPU cycle FREQ : relation to nominal CPU frequency='unhalted clock ticks'/'invariant timer ticks' (includes Intel Turbo Boost) AFREQ : relation to nominal CPU frequency while in active state (not in power-saving C state)='unhalted clock ticks'/'invariant timer ticks while in C0-state' (includes Intel Turbo Boost) L3MISS: L3 cache misses L2MISS: L2 cache misses (including other core's L2 cache *hits*) L3HIT : L3 cache hit ratio (0.00-1.00) L2HIT : L2 cache hit ratio (0.00-1.00) L3CLK : ratio of CPU cycles lost due to L3 cache misses (0.00-1.00), in some cases could be >1.0 due to a higher memory latency L2CLK : ratio of CPU cycles lost due to missing L2 cache but still hitting L3 cache (0.00-1.00) READ : bytes read from memory controller (in GBytes) WRITE : bytes written to memory controller (in GBytes) IO : bytes read/written due to IO requests to memory controller (in GBytes); this may be an over estimate due to same-cache-line partial requests TEMP : Temperature reading in 1 degree Celsius relative to the TjMax temperature (thermal headroom): 0 corresponds to the max temperature Core (SKT) | EXEC | IPC | FREQ | AFREQ | L3MISS | L2MISS | L3HIT | L2HIT | L3CLK | L2CLK | READ | WRITE | IO | TEMP | 0 0 0.00 0.23 0.00 0.55 21 K 23 K 0.08 0.01 1.00 0.02 N/A N/A N/A 75 1 0 0.00 0.29 0.00 0.55 4206 4322 0.03 0.01 1.71 0.01 N/A N/A N/A 75 2 0 0.00 0.52 0.00 0.55 6786 7009 0.03 0.00 1.17 0.01 N/A N/A N/A 75 3 0 0.00 0.22 0.00 0.55 7329 7673 0.04 0.00 1.63 0.02 N/A N/A N/A 75 4 0 0.00 0.21 0.00 0.55 45 K 51 K 0.12 0.00 1.39 0.04 N/A N/A N/A 75 5 0 0.00 0.33 0.00 0.55 11 K 11 K 0.03 0.09 1.39 0.01 N/A N/A N/A 75 6 0 0.00 0.34 0.00 0.55 23 K 26 K 0.09 0.00 0.99 0.02 N/A N/A N/A 75 7 0 0.00 0.62 0.00 0.55 11 K 11 K 0.01 0.07 1.22 0.00 N/A N/A N/A 75 ----------------------------------------------------------------------------------------------------------------------------- SKT 0 0.00 0.30 0.00 0.55 131 K 143 K 0.08 0.02 1.22 0.02 0.37 0.00 0.36 74 ----------------------------------------------------------------------------------------------------------------------------- TOTAL * 0.00 0.30 0.00 0.55 131 K 143 K 0.08 0.02 1.22 0.02 0.37 0.00 0.36 N/A Instructions retired: 5917 K ; Active cycles: 19 M ; Time (TSC): 2335 Mticks ; C0 (active,non-halted) core residency: 0.19 % C1 core residency: 0.25 %; C3 core residency: 0.00 %; C6 core residency: 0.00 %; C7 core residency: 99.56 %; C2 package residency: 1.15 %; C3 package residency: 0.00 %; C6 package residency: 0.63 %; C7 package residency: 96.61 %; PHYSICAL CORE IPC : 0.61 => corresponds to 15.18 % utilization for cores in active state Instructions per nominal CPU cycle: 0.00 => corresponds to 0.02 % core utilization over time interval ---------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------- SKT 0 package consumed 3.33 Joules ---------------------------------------------------------------------------------------------- TOTAL: 3.33 Joules ^CDEBUG: caught signal to interrupt (Interrupt). Cleaning up Zeroed PMU registers Freeing up all RMIDs
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