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  1. /*
  2.  * sense.v
  3.  *
  4.  * vim: ts=4 sw=4
  5.  *
  6.  * Copyright (C) 2019  Sylvain Munaut <tnt@246tNt.com>
  7.  * All rights reserved.
  8.  *
  9.  * BSD 3-clause, see LICENSE.bsd
  10.  *
  11.  * Redistribution and use in source and binary forms, with or without
  12.  * modification, are permitted provided that the following conditions are met:
  13.  *     * Redistributions of source code must retain the above copyright
  14.  *       notice, this list of conditions and the following disclaimer.
  15.  *     * Redistributions in binary form must reproduce the above copyright
  16.  *       notice, this list of conditions and the following disclaimer in the
  17.  *       documentation and/or other materials provided with the distribution.
  18.  *     * Neither the name of the <organization> nor the
  19.  *       names of its contributors may be used to endorse or promote products
  20.  *       derived from this software without specific prior written permission.
  21.  *
  22.  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  23.  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24.  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  25.  * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
  26.  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  27.  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  28.  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  29.  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  31.  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32.  */
  33.  
  34. `default_nettype none
  35.  
  36. module sense (
  37.     // Sense IO
  38.     output reg  sense_ctrl,
  39.     output reg  [3:0] sense_mux,
  40.     output reg  sense_ena_n,
  41.     inout  wire sense_hi,
  42. //  inout  wire sense_lo,
  43.  
  44.     // Control
  45.     input  wire [3:0] ctrl_chan,
  46.     input  wire ctrl_go,
  47.     output wire ctrl_rdy,
  48.  
  49.     output reg  [17:0] meas_chg,
  50.     output wire [17:0] meas_dis,
  51.     output wire meas_stb,
  52.  
  53.     // Debug
  54.     output wire debug,
  55.  
  56.     // Clock / Reset
  57.     input  wire clk,
  58.     input  wire rst
  59. );
  60.  
  61.     // Signals
  62.     // -------
  63.  
  64.     // FSM
  65.     localparam
  66.         ST_IDLE      = 0,
  67.         ST_SETUP     = 1,
  68.         ST_CHARGE    = 2,
  69.         ST_DISCHARGE = 3;
  70.  
  71.     reg [1:0] state;
  72.     reg [1:0] state_nxt;
  73.  
  74.     // Timer
  75.     reg  [17:0] timer;
  76.     wire timer_trig;
  77.  
  78.     // IOB
  79.     wire [1:0] sense_iob;
  80.     reg  [1:0] sense_val;
  81.  
  82.     // Counter
  83.     reg  [17:0] sense_cnt;
  84.  
  85.  
  86.     // FSM
  87.     // ---
  88.  
  89.     always @(posedge clk or posedge rst)
  90.         if (rst)
  91.             state <= ST_IDLE;
  92.         else
  93.             state <= state_nxt;
  94.  
  95.     always @(*)
  96.     begin
  97.         state_nxt = state;
  98.  
  99.         case (state_nxt)
  100.             ST_IDLE:
  101.                 if (ctrl_go)
  102.                     state_nxt = ST_SETUP;
  103.  
  104.             ST_SETUP:
  105.                 if (timer_trig)
  106.                     state_nxt = ST_CHARGE;
  107.  
  108.             ST_CHARGE:
  109.                 if (timer_trig)
  110.                     state_nxt = ST_DISCHARGE;
  111.  
  112.             ST_DISCHARGE:
  113.                 if (timer_trig)
  114.                     state_nxt = ST_IDLE;
  115.         endcase
  116.     end
  117.  
  118.  
  119.     // Timers
  120.     // ------
  121.  
  122.     always @(posedge clk)
  123.         if (state == ST_IDLE)
  124. //          timer <= 18'h1f800;     // 2049 cycles ( ~ 42 us )
  125.             timer <= 18'h18000;     // 2049 cycles ( ~ 42 us )
  126.         else if (timer_trig)
  127.             timer <= 18'h00000;     // 131073 cycle ( 2.7306875 ms )
  128.         else
  129.             timer <= timer + 1;
  130.  
  131.     assign timer_trig = timer[17];
  132.  
  133.  
  134.     // Sense IO
  135.     // --------
  136.  
  137.     SB_IO #(
  138.         .PIN_TYPE(6'b0000_00),
  139.         .IO_STANDARD("SB_LVDS_INPUT"),
  140.         .PULLUP(1'b0),
  141.         .NEG_TRIGGER(1'b0)
  142.     ) SB_IO (
  143.         .PACKAGE_PIN(sense_hi),
  144.         .INPUT_CLK(clk),
  145.         .D_IN_0(sense_iob[0]),
  146.         .D_IN_1(sense_iob[1])
  147.     );
  148.  
  149.     always @(posedge clk)
  150.         sense_val <= {
  151.             sense_iob[0] & sense_iob[1],
  152.             sense_iob[0] ^ sense_iob[1]
  153.         };
  154.  
  155.     assign debug = sense_iob[0];
  156.  
  157.  
  158.     // Measurement counters
  159.     // --------------------
  160.  
  161.     always @(posedge clk)
  162.         if (timer_trig)
  163.             sense_cnt <= 0;
  164.         else
  165.             sense_cnt <= sense_cnt + sense_val;
  166.  
  167.  
  168.     // Control hardware
  169.     // ----------------
  170.  
  171.     always @(posedge clk or posedge rst)
  172.     begin
  173.         if (rst) begin
  174.             sense_ctrl  <= 1'b0;
  175.             sense_mux   <= 4'h0;    // GND
  176.             sense_ena_n <= 1'b1;    // Disabled
  177.         end else begin
  178.             // Setup analog mux
  179.             if (state == ST_IDLE) begin
  180.                 sense_mux   <= ctrl_go ? ctrl_chan : 4'h0;
  181.                 sense_ena_n <= ~ctrl_go;
  182.             end
  183.  
  184.             // Charge // discharge
  185.             sense_ctrl <= (state_nxt == ST_CHARGE);
  186.         end
  187.     end
  188.  
  189.  
  190.     // User IF
  191.     // -------
  192.  
  193.     assign ctrl_rdy = (state == ST_IDLE);
  194.  
  195.     always @(posedge clk)
  196.         if ((state == ST_CHARGE) & timer_trig)
  197.             meas_chg <= sense_cnt;
  198.  
  199.     assign meas_dis = sense_cnt;
  200.  
  201.     assign meas_stb = (state == ST_DISCHARGE) & timer_trig;
  202.  
  203. endmodule // sense
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