module dithgen(

    input clk,
    output logic [1:0] out

    );

logic [15:0] lfsrA;
logic [15:0] lfsrB;

wire feedbackA;
wire feedbackB;

assign feedbackA = !(lfsrA[2] ^ lfsrA[11] ^ lfsrA[14]);
assign feedbackB = !(lfsrB[3] ^ lfsrB[10] ^ lfsrB[15]);

initial begin

    lfsrA = 16'hABCD;
    lfsrB = 16'h1234;

end


always @ (posedge clk) begin

    lfsrA <= {lfsrA[14:0], feedbackA};
    lfsrB <= {lfsrB[14:0], feedbackB};

end

assign out = lfsrA[3:2] + lfsrB[3:2];

endmodule