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  1. [azl@fedora gateware]$ make -C . -f /home/azl/Code/litex/litex/litex/build/sim/core/Makefile CC_SRCS="--cc /home/azl/Code/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/sim.v "   OPT_LEVEL=O3
  2. make: Entering directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware'
  3. mkdir -p modules
  4. make -C modules -f /home/azl/Code/litex/litex/litex/build/sim/core/modules/Makefile
  5. make[1]: Entering directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/modules'
  6. mkdir -p xgmii_ethernet
  7. make MOD=xgmii_ethernet -C xgmii_ethernet -f /home/azl/Code/litex/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile
  8. make[2]: Entering directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/modules/xgmii_ethernet'
  9. make[2]: Nothing to be done for 'all'.
  10. make[2]: Leaving directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/modules/xgmii_ethernet'
  11. cp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so
  12. mkdir -p ethernet
  13. make MOD=ethernet -C ethernet -f /home/azl/Code/litex/litex/litex/build/sim/core/modules/ethernet/Makefile
  14. make[2]: Entering directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/modules/ethernet'
  15. make[2]: Nothing to be done for 'all'.
  16. make[2]: Leaving directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/modules/ethernet'
  17. cp ethernet/ethernet.so ethernet.so
  18. mkdir -p serial2console
  19. make MOD=serial2console -C serial2console -f /home/azl/Code/litex/litex/litex/build/sim/core/modules/serial2console/Makefile
  20. make[2]: Entering directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/modules/serial2console'
  21. make[2]: Nothing to be done for 'all'.
  22. make[2]: Leaving directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/modules/serial2console'
  23. cp serial2console/serial2console.so serial2console.so
  24. mkdir -p serial2tcp
  25. make MOD=serial2tcp -C serial2tcp -f /home/azl/Code/litex/litex/litex/build/sim/core/modules/serial2tcp/Makefile
  26. make[2]: Entering directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/modules/serial2tcp'
  27. make[2]: Nothing to be done for 'all'.
  28. make[2]: Leaving directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/modules/serial2tcp'
  29. cp serial2tcp/serial2tcp.so serial2tcp.so
  30. mkdir -p clocker
  31. make MOD=clocker -C clocker -f /home/azl/Code/litex/litex/litex/build/sim/core/modules/clocker/Makefile
  32. make[2]: Entering directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/modules/clocker'
  33. make[2]: Nothing to be done for 'all'.
  34. make[2]: Leaving directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/modules/clocker'
  35. cp clocker/clocker.so clocker.so
  36. mkdir -p spdeeprom
  37. make MOD=spdeeprom -C spdeeprom -f /home/azl/Code/litex/litex/litex/build/sim/core/modules/spdeeprom/Makefile
  38. make[2]: Entering directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/modules/spdeeprom'
  39. make[2]: Nothing to be done for 'all'.
  40. make[2]: Leaving directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/modules/spdeeprom'
  41. cp spdeeprom/spdeeprom.so spdeeprom.so
  42. make[1]: Leaving directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/modules'
  43. mkdir -p /home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/obj_dir
  44. cc -c -ggdb -Wall -O3   -o /home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/obj_dir/libdylib.o /home/azl/Code/litex/litex/litex/build/sim/core/libdylib.c
  45. cc -c -ggdb -Wall -O3   -o /home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/obj_dir/modules.o /home/azl/Code/litex/litex/litex/build/sim/core/modules.c
  46. In file included from /home/azl/Code/litex/litex/litex/build/sim/core/modules.c:6:
  47. In function ‘tinydir_readfile’,
  48.     inlined from ‘litex_sim_load_ext_modules’ at /home/azl/Code/litex/litex/litex/build/sim/core/modules.c:68:14:
  49. /home/azl/Code/litex/litex/litex/build/sim/core/tinydir.h:81:25: warning: ‘strcat’ accessing 4097 or more bytes at offsets 0 and 4096 may overlap 1 byte at offset 4096 [-Wrestrict]
  50.    81 | #define _tinydir_strcat strcat
  51.       |                         ^
  52. /home/azl/Code/litex/litex/litex/build/sim/core/tinydir.h:532:9: note: in expansion of macro ‘_tinydir_strcat’
  53.   532 |         _tinydir_strcat(file->path, file->name);
  54.       |         ^~~~~~~~~~~~~~~
  55. cc -c -ggdb -Wall -O3   -o /home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/obj_dir/pads.o /home/azl/Code/litex/litex/litex/build/sim/core/pads.c
  56. cc -c -ggdb -Wall -O3   -o /home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/obj_dir/parse.o /home/azl/Code/litex/litex/litex/build/sim/core/parse.c
  57. cc -c -ggdb -Wall -O3   -o /home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/obj_dir/sim.o /home/azl/Code/litex/litex/litex/build/sim/core/sim.c
  58. verilator -Wno-fatal -O3 --cc /home/azl/Code/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/sim.v  --top-module sim --exe \
  59.         -DPRINTF_COND=0 \
  60.         sim_init.cpp /home/azl/Code/litex/litex/litex/build/sim/core/veril.cpp libdylib.o modules.o pads.o parse.o sim.o \
  61.         --top-module sim \
  62.          \
  63.         -CFLAGS "-ggdb -Wall -O3   -I/home/azl/Code/litex/litex/litex/build/sim/core" \
  64.         -LDFLAGS "-lpthread -Wl,--no-as-needed -ljson-c -lm -lstdc++ -Wl,--no-as-needed -ldl -levent" \
  65.         --trace \
  66.          \
  67.          \
  68.         --unroll-count 256 \
  69.         --output-split 5000 \
  70.         --output-split-cfuncs 500 \
  71.         --output-split-ctrace 500 \
  72.          \
  73.         -Wno-BLKANDNBLK \
  74.         -Wno-WIDTH
  75. make -j -C /home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/obj_dir -f Vsim.mk Vsim
  76. make[1]: Entering directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/obj_dir'
  77. g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -ggdb -Wall -O3   -I/home/azl/Code/litex/litex/litex/build/sim/core  -std=gnu++14 -Os -c -o verilated.o /usr/share/verilator/include/verilated.cpp
  78. Archive ar -cr Vsim__ALL.a Vsim.o Vsim_sim.o Vsim_VexRiscv.o Vsim_VexRiscv__1.o Vsim_VexRiscv__2.o Vsim__Dpi.o Vsim__Trace.o Vsim__Slow.o Vsim_sim__Slow.o Vsim_VexRiscv__Slow.o Vsim_VexRiscv__1__Slow.o Vsim__Syms.o Vsim__Trace__Slow.o Vsim__Trace__1__Slow.o
  79. /usr/share/verilator/include/verilated.cpp: In function ‘IData VL_FGETS_NI(std::string&, IData)’:
  80. /usr/share/verilator/include/verilated.cpp:1318:36: error: ‘numeric_limits’ is not a member of ‘std’
  81.  1318 |     return getLine(dest, fpi, std::numeric_limits<size_t>::max());
  82.       |                                    ^~~~~~~~~~~~~~
  83. /usr/share/verilator/include/verilated.cpp:1318:57: error: expected primary-expression before ‘>’ token
  84.  1318 |     return getLine(dest, fpi, std::numeric_limits<size_t>::max());
  85.       |                                                         ^
  86. /usr/share/verilator/include/verilated.cpp:1318:60: error: ‘::max’ has not been declared; did you mean ‘std::max’?
  87.  1318 |     return getLine(dest, fpi, std::numeric_limits<size_t>::max());
  88.       |                                                            ^~~
  89.       |                                                            std::max
  90. In file included from /usr/include/c++/11/algorithm:62,
  91.                  from /usr/share/verilator/include/verilated_heavy.h:29,
  92.                  from /usr/share/verilator/include/verilated_imp.h:29,
  93.                  from /usr/share/verilator/include/verilated.cpp:25:
  94. /usr/include/c++/11/bits/stl_algo.h:3467:5: note: ‘std::max’ declared here
  95.  3467 |     max(initializer_list<_Tp> __l, _Compare __comp)
  96.       |     ^~~
  97. make[1]: *** [/usr/share/verilator/include/verilated.mk:241: verilated.o] Error 1
  98. make[1]: Leaving directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware/obj_dir'
  99. make: *** [/home/azl/Code/litex/litex/litex/build/sim/core/Makefile:39: sim] Error 2
  100. make: Leaving directory '/home/azl/Code/litex/litex/litex/soc/software/demo/build/sim/gateware'
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