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  1. �SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;CHK:1F;READ:0;CHK:1F;SD?:0;SD:0;READ:0;
  2. bl2_stage_init 0x01
  3. bl2_stage_init 0x81
  4. hw id: 0x0000 - pwm id 0x01
  5. bl2_stage_init 0xc1
  6. bl2_stage_init 0x02
  7.  
  8. no sdio debug board detected
  9. L0:00000000
  10. L1:00000703
  11. L2:00008067
  12. L3:15000020
  13. S1:00000000
  14. B2:20282000
  15. B1:a0f83180
  16.  
  17. TE: 340033
  18.  
  19. BL2 Built : 15:21:42, Mar 26 2020. g12a g486bc38 - gongwei.chen@droid11-sz
  20.  
  21. Board ID = 1
  22. Set cpu clk to 24M
  23. Set clk81 to 24M
  24. Use GP1_pll as DSU clk.
  25. DSU clk: 1200 Mhz
  26. CPU clk: 1200 MHz
  27. Set clk81 to 166.6M
  28. board id: 1
  29. Load FIP HDR DDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
  30. fw parse done
  31. PIEI prepare done
  32. fastboot data verify
  33. result: 255
  34. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  35. DDR4 probe
  36.  
  37. LPDDR4_PHY_V_0_1_21-Built : 15:37:51, Mar 26 2020. g12a gf098346 - gongwei.chen@droid11-sz
  38. ddr clk to 1320MHz
  39.  
  40. dmc_version 0001
  41. Check phy result
  42. INFO : End of initialization
  43. INFO : ERROR : Training has failed!
  44. 1D training failed
  45. Cfg max: 12, cur: 2. Board id: 255. Force loop cfg
  46. LPDDR4 probe
  47. ddr clk to 1392MHz
  48.  
  49. dmc_version 0001
  50. Check phy result
  51. INFO : End of CA training
  52. INFO : End of initialization
  53. INFO : Training has run successfully!
  54. Check phy result
  55. INFO : End of initialization
  56. INFO : End of read enable training
  57. INFO : End of fine write leveling
  58. INFO : End of Write leveling coarse delay
  59. INFO : Training has run successfully!
  60. Check phy result
  61. INFO : End of initialization
  62. INFO : End of read dq deskew training
  63. INFO : End of MPR read delay center optimization
  64. INFO : End of write delay center optimization
  65. INFO : End of read delay center optimization
  66. INFO : End of max read latency training
  67. INFO : Training has run successfully!
  68. 1D training succeed
  69. Check phy result
  70. INFO : End of initialization
  71. INFO : End of 2D read delay Voltage center optimization
  72. INFO : End of 2D read delay Voltage center optimization
  73. INFO : End of 2D write delay Voltage center optimization
  74. INFO : End of 2D write delay Voltage center optimization
  75. INFO : Training has run successfully!
  76.  
  77. soc_vref_reg_value 0x 00000011 00000016 00000014 00000013 00000013 00000014 00000013 00000013 00000016 00000013 00000014 00
  78. dram_vref_reg_value 0x 00000061
  79. 2D training succeed
  80. auto size-- 65535DDR cs0 size: 2048MB
  81. DDR cs1 size: 2048MB
  82. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  83. cs0 DataBus test pass
  84. cs1 DataBus test pass
  85. cs0 AddrBus test pass
  86. cs1 AddrBus test pass
  87.  
  88. non-sec scramble use zero key
  89. ddr scramble enabled
  90.  
  91. 100bdlr_step_size ps== 382
  92. result report
  93. boot times 0Enable ddr reg access
  94. Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  95. Load BL3X from SD, src: 0x00078200, des: 0x01768000, size: 0x00098400, part: 0
  96. 0.0;M3 CHK:0;cm4_sp_mode 0
  97. MVN_1=0x00000000
  98. MVN_2=0x00000000
  99. [Image: g12a_v1.1.3386-3b31431 2019-05-21 10:41:54 luan.yuan@droid15-sz]
  100. OPS=0x10
  101. ring efuse init
  102. 2b 0c 10 00 01 24 12 00 00 10 38 31 56 52 52 50
  103. [0.017318 Inits done]
  104. secure task start!
  105. high task start!
  106. low task start!
  107. boot bl31
  108. NOTICE: BL31: v1.3(release):4fc40b1
  109. NOTICE: BL31: Built : 15:57:33, May 22 2019
  110. NOTICE: BL31: G12A normal boot!
  111. NOTICE: BL31: BL33 decompress pass
  112. ERROR: Error initializing runtime service opteed_fast
  113.  
  114.  
  115. U-Boot 2021.10-rc2 (Nov 02 2021 - 12:07:05 -0500)bpi-m5
  116.  
  117. Model: Banana Pi BPI-M5
  118. SoC: Amlogic Meson SM1 (S905X3) Revision 2b:c (10:2)
  119. DRAM: 3.8 GiB
  120. MMC: sd@ffe05000: 0, mmc@ffe07000: 1
  121. Loading Environment from nowhere... OK
  122. In: serial
  123. Out: serial
  124. Err: serial
  125. Net: eth0: ethernet@ff3f0000
  126. Hit any key to stop autoboot: 0
  127. switch to partitions #0, OK
  128. mmc0 is current device
  129. Scanning mmc 0:1...
  130. Found U-Boot script /boot.scr
  131. 1061 bytes read in 1 ms (1 MiB/s)
  132. ## Executing script at 08000000
  133. BOOT DEVICE: SD
  134. BOOT PATH: /dev/mmcblk0p2
  135. 14134629 bytes read in 604 ms (22.3 MiB/s)
  136. 19911168 bytes read in 850 ms (22.3 MiB/s)
  137. 73627 bytes read in 6 ms (11.7 MiB/s)
  138. Moving Image from 0x8080000 to 0x8200000, end=9580000
  139. ## Loading init Ramdisk from Legacy Image at 13000000 ...
  140. Image Name: uInitrd
  141. Image Type: AArch64 Linux RAMDisk Image (gzip compressed)
  142. Data Size: 14134565 Bytes = 13.5 MiB
  143. Load Address: 00000000
  144. Entry Point: 00000000
  145. Verifying Checksum ... OK
  146. ## Flattened Device Tree blob at 08008000
  147. Booting using the fdt blob at 0x8008000
  148. Loading Ramdisk to 3f285000, end 3ffffd25 ... OK
  149. Loading Device Tree to 000000003f20a000, end 000000003f284fff ... OK
  150.  
  151. Starting kernel ...
  152.  
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