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- �SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;READ:0;CHK:1F;READ:0;CHK:1F;SD?:0;SD:0;READ:0;
- bl2_stage_init 0x01
- bl2_stage_init 0x81
- hw id: 0x0000 - pwm id 0x01
- bl2_stage_init 0xc1
- bl2_stage_init 0x02
- no sdio debug board detected
- L0:00000000
- L1:00000703
- L2:00008067
- L3:15000020
- S1:00000000
- B2:20282000
- B1:a0f83180
- TE: 340033
- BL2 Built : 15:21:42, Mar 26 2020. g12a g486bc38 - gongwei.chen@droid11-sz
- Board ID = 1
- Set cpu clk to 24M
- Set clk81 to 24M
- Use GP1_pll as DSU clk.
- DSU clk: 1200 Mhz
- CPU clk: 1200 MHz
- Set clk81 to 166.6M
- board id: 1
- Load FIP HDR DDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
- fw parse done
- PIEI prepare done
- fastboot data verify
- result: 255
- Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
- DDR4 probe
- LPDDR4_PHY_V_0_1_21-Built : 15:37:51, Mar 26 2020. g12a gf098346 - gongwei.chen@droid11-sz
- ddr clk to 1320MHz
- dmc_version 0001
- Check phy result
- INFO : End of initialization
- INFO : ERROR : Training has failed!
- 1D training failed
- Cfg max: 12, cur: 2. Board id: 255. Force loop cfg
- LPDDR4 probe
- ddr clk to 1392MHz
- dmc_version 0001
- Check phy result
- INFO : End of CA training
- INFO : End of initialization
- INFO : Training has run successfully!
- Check phy result
- INFO : End of initialization
- INFO : End of read enable training
- INFO : End of fine write leveling
- INFO : End of Write leveling coarse delay
- INFO : Training has run successfully!
- Check phy result
- INFO : End of initialization
- INFO : End of read dq deskew training
- INFO : End of MPR read delay center optimization
- INFO : End of write delay center optimization
- INFO : End of read delay center optimization
- INFO : End of max read latency training
- INFO : Training has run successfully!
- 1D training succeed
- Check phy result
- INFO : End of initialization
- INFO : End of 2D read delay Voltage center optimization
- INFO : End of 2D read delay Voltage center optimization
- INFO : End of 2D write delay Voltage center optimization
- INFO : End of 2D write delay Voltage center optimization
- INFO : Training has run successfully!
- soc_vref_reg_value 0x 00000011 00000016 00000014 00000013 00000013 00000014 00000013 00000013 00000016 00000013 00000014 00
- dram_vref_reg_value 0x 00000061
- 2D training succeed
- auto size-- 65535DDR cs0 size: 2048MB
- DDR cs1 size: 2048MB
- DMC_DDR_CTRL: 00e00024DDR size: 3928MB
- cs0 DataBus test pass
- cs1 DataBus test pass
- cs0 AddrBus test pass
- cs1 AddrBus test pass
- non-sec scramble use zero key
- ddr scramble enabled
- 100bdlr_step_size ps== 382
- result report
- boot times 0Enable ddr reg access
- Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
- Load BL3X from SD, src: 0x00078200, des: 0x01768000, size: 0x00098400, part: 0
- 0.0;M3 CHK:0;cm4_sp_mode 0
- MVN_1=0x00000000
- MVN_2=0x00000000
- [Image: g12a_v1.1.3386-3b31431 2019-05-21 10:41:54 luan.yuan@droid15-sz]
- OPS=0x10
- ring efuse init
- 2b 0c 10 00 01 24 12 00 00 10 38 31 56 52 52 50
- [0.017318 Inits done]
- secure task start!
- high task start!
- low task start!
- boot bl31
- NOTICE: BL31: v1.3(release):4fc40b1
- NOTICE: BL31: Built : 15:57:33, May 22 2019
- NOTICE: BL31: G12A normal boot!
- NOTICE: BL31: BL33 decompress pass
- ERROR: Error initializing runtime service opteed_fast
- U-Boot 2021.10-rc2 (Nov 02 2021 - 12:07:05 -0500)bpi-m5
- Model: Banana Pi BPI-M5
- SoC: Amlogic Meson SM1 (S905X3) Revision 2b:c (10:2)
- DRAM: 3.8 GiB
- MMC: sd@ffe05000: 0, mmc@ffe07000: 1
- Loading Environment from nowhere... OK
- In: serial
- Out: serial
- Err: serial
- Net: eth0: ethernet@ff3f0000
- Hit any key to stop autoboot: 0
- switch to partitions #0, OK
- mmc0 is current device
- Scanning mmc 0:1...
- Found U-Boot script /boot.scr
- 1061 bytes read in 1 ms (1 MiB/s)
- ## Executing script at 08000000
- BOOT DEVICE: SD
- BOOT PATH: /dev/mmcblk0p2
- 14134629 bytes read in 604 ms (22.3 MiB/s)
- 19911168 bytes read in 850 ms (22.3 MiB/s)
- 73627 bytes read in 6 ms (11.7 MiB/s)
- Moving Image from 0x8080000 to 0x8200000, end=9580000
- ## Loading init Ramdisk from Legacy Image at 13000000 ...
- Image Name: uInitrd
- Image Type: AArch64 Linux RAMDisk Image (gzip compressed)
- Data Size: 14134565 Bytes = 13.5 MiB
- Load Address: 00000000
- Entry Point: 00000000
- Verifying Checksum ... OK
- ## Flattened Device Tree blob at 08008000
- Booting using the fdt blob at 0x8008000
- Loading Ramdisk to 3f285000, end 3ffffd25 ... OK
- Loading Device Tree to 000000003f20a000, end 000000003f284fff ... OK
- Starting kernel ...
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