library ieee;
use ieee.std_logic_1164.all;

entity hex7seg is
	port (
		hex : integer range 0 to 15;
		display : out STD_LOGIC_VECTOR(0 to 6)
	);
end hex7seg;

architecture behhex7seg of hex7seg is
begin
	process (hex)
	begin
		case hex is
			WHEN 0 => display <= "0000001";
			WHEN 1 => display <= "1001111";
			WHEN 2 => display <= "0010010";
			WHEN 3 => display <= "0000110";
			WHEN 4 => display <= "1001100";
			WHEN 5 => display <= "0100100";
			WHEN 6 => display <= "0100000";
			WHEN 7 => display <= "0001111";
			WHEN 8 => display <= "0000000";
			WHEN OTHERS => display <= "0000100";
		end case;
	end process;
end behhex7seg;

library ieee;
use ieee.std_logic_1164.all;

entity licznik is
	port(
		CLK : in std_logic;
		HEX0 : out std_logic_vector(0 to 6)
	);
end licznik;

architecture behlicznik of licznik is

component hex7seg is
	port(
		hex : integer range 0 to 15;
		display: out std_logic_vector(0 to 6)
	);
end component;

constant countLimit : integer := 50000000;
signal currentCount : integer range 0 to 214748364 := 0;
signal digit : integer range 0 to 15 := 0;
signal digit2 : integer range 0 to 15 := 0;
signal HEXTMP : std_logic_vector (0 to 6);
signal HEXTMP2 : std_logic_vector (0 to 6);

begin
	SEG0 : hex7seg port map(hex=>digit, display=>HEXTMP);
	SEG1 : hex7seg port map(hex=>digit2, display=>HEXTMP);

	process1 : process(CLK)
		begin
		if(CLK'event and CLK = '0')
		then currentCount <= currentCount + 1;
		end if;

		if (currentCount >= countLimit) then
		if(digit <9) then
		digit <= digit +1;
		else
		digit<=0;
			if (digi2 < 5) then

		end if;
		currentCount <= 0;
		end if;
		end process;

	process2: process(digit)
		begin
		HEX0 <= HEXTMP;
		end process;

	process3: process(digit)
		begin
		HEX1 <= HEXTMP2;
		end process;
end behlicznik;