LAC adder

//https://verilogcodes.blogspot.com/2017/11/verilog-code-for-carry-look-ahead-adder.html
//https://verilogcodes.blogspot.com/2017/11/verilog-code-for-carry-select-adder.html
//http://techmasterplus.com/programs/verilog/claadder.php?i=1
////////////////////////////////cla_adder.v
module cla_adder
        (   input [3:0] A,B,
            input cin,
            output [3:0] S,
            output cout
            );

wire [3:0] P,G;
wire [4:0] C;

//first level
assign P = A ^ B;
assign G = A & B;

//second level
cla_block gen_c(P,G,cin,C);

//third level
assign S = P ^ C[3:0];
assign cout = C[4];

endmodule


//////////////////////////////////////////////////cla_block.v
module cla_block
        (   input [3:0] P,G,
            input cin,
            output [4:0] C
            );

assign C[0] = cin;
assign C[1] = G[0] | (P[0] & cin);
assign C[2] = G[1] | (P[1] & G[0]) | (P[1] & P[0] & cin);
assign C[3] = G[2] | (P[2] & G[1]) | (P[2] & P[1] & G[0]) | (P[2] & P[1] & P[0] & cin);
assign C[4] = G[3] | (P[3] & G[2]) | (P[3] & P[2] & G[1]) |
            (P[3] & P[2] & P[1] & G[0]) | (P[3] & P[2] & P[1] & P[0] & cin);

endmodule


/////////////////////////////////////////////////////////////// otro

///////////////////////////////////////////////////////////////////////////
// Company: TMP
// Create Date: 08:15:45 01/12/2015
// Module Name: CLA_Adder
// Project Name: Carry Look Ahead Adder
///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
// Company: TMP
// Create Date: 08:15:45 01/12/2015
// Module Name: CLA_Adder
// Project Name: Carry Look Ahead Adder
///////////////////////////////////////////////////////////////////////////
module CLA_Adder(a,b,cin,sum,cout);
input[3:0] a,b;
input cin;
output [3:0] sum;
output cout;
wire p0,p1,p2,p3,g0,g1,g2,g3,c1,c2,c3,c4;
assign p0=(a[0]^b[0]),
p1=(a[1]^b[1]),
p2=(a[2]^b[2]),
p3=(a[3]^b[3]);
assign g0=(a[0]&b[0]),
g1=(a[1]&b[1]),
g2=(a[2]&b[2]),
g3=(a[3]&b[3]);
assign c0=cin,
c1=g0|(p0&cin),
c2=g1|(p1&g0)|(p1&p0&cin),
c3=g2|(p2&g1)|(p2&p1&g0)|(p1&p1&p0&cin),
c4=g3|(p3&g2)|(p3&p2&g1)|(p3&p2&p1&g0)|(p3&p2&p1&p0&cin);
assign sum[0]=p0^c0,
sum[1]=p1^c1,
sum[2]=p2^c2,
sum[3]=p3^c3;
assign cout=c4;
endmodule
//////////////// testbe
module TestModule;
// Inputs
reg [3:0] a;
reg [3:0] b;
reg cin;

// Outputs
wire [3:0] sum;
wire cout;

// Instantiate the Unit Under Test (UUT)
CLA_Adder uut (
.a(a),
.b(b),
.cin(cin),
.sum(sum),
.cout(cout)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
cin = 0;
// Wait 100 ns for global reset to finish
#100;
a = 5;
b = 6;
cin = 1;
// Wait 100 ns for global reset to finish
#100;
end
endmodule