module test(x1,x2,x3,y1,y2);

input x1,x2,x3;
output reg y1,y2;

// module 1
always @ (x1 or y1)
begin

    if (x1 == 0)
        y1 = 0;
    else
        y1 = 1;

end

// module 2
always @ (x2 or x3 or y2)
begin

   y2 = x2 | ~x3;

end

endmodule