// Code generated by Icestudio 0.3.0-beta2
// Sun, 05 Feb 2017 02:07:00 GMT

`default_nettype none

module main #(
 parameter vcd7809 = 350,
 parameter v23063d = 700,
 parameter v5fb649 = 800,
 parameter vfbbfd8 = 600,
 parameter v528657 = 100000,
 parameter v7c6d55 = 0.012,
 parameter vdc851f = 150
) (
 input vb94c31,
 output v4b594f,
 output v6f57a9
);
 localparam p0 = vfbbfd8;
 localparam p1 = v528657;
 localparam p2 = v7c6d55;
 localparam p3 = vdc851f;
 localparam p4 = v5fb649;
 localparam p5 = v23063d;
 localparam p6 = vcd7809;
 wire w7;
 wire [0:31] w8;
 wire [0:23] w9;
 wire w10;
 wire w11;
 wire w12;
 wire w13;
 wire w14;
 wire w15;
 wire w16;
 assign w12 = vb94c31;
 assign w13 = vb94c31;
 assign v6f57a9 = w14;
 assign v4b594f = w16;
 assign w13 = w12;
 assign w16 = w7;
 main_v862d2a vdb48fe (
  .v608bd9(w15)
 );
 main_v372cbb #(
  .T1L(p0),
  .RST(p1),
  .MASTER_CLK(p2),
  .NB_LEDS(p3),
  .T1H(p4),
  .T0L(p5),
  .T0H(p6)
 ) v372cbb (
  .busy(w7),
  .addr(w8),
  .value(w9),
  .display(w10),
  .write(w11),
  .clk(w12),
  .led_out(w14),
  .reset(w15)
 );
 main_vc85087 vc85087 (
  .busy(w7),
  .addr(w8),
  .value(w9),
  .display(w10),
  .write(w11),
  .clk(w13)
 );
endmodule

module main_v862d2a (
 output v608bd9
);
 wire w0;
 assign v608bd9 = w0;
 main_v862d2a_v68c173 v68c173 (
  .v(w0)
 );
endmodule

module main_v862d2a_v68c173 (
 output v
);
 // Bit 0

 assign v = 1'b0;
endmodule

module main_v372cbb #(
 parameter T0H = 0,
 parameter T0L = 0,
 parameter T1H = 0,
 parameter T1L = 0,
 parameter RST = 0,
 parameter MASTER_CLK = 0,
 parameter NB_LEDS = 0
) (
 input clk,
 input reset,
 input write,
 input [31:0] addr,
 input [23:0] value,
 input display,
 output busy,
 output led_out
);
 localparam MASTER_PERIOD        = 1 / MASTER_CLK;
 localparam integer T0H_C                = T0H / MASTER_PERIOD;
 localparam integer T1H_C                = T1H / MASTER_PERIOD;
 localparam integer T0L_C                = T0L / MASTER_PERIOD;
 localparam integer T1L_C                = T1L / MASTER_PERIOD;
 localparam integer RST_C                = RST / MASTER_PERIOD;

 // Modification because no output reg
 reg r_led_out = 0;
 assign led_out = r_led_out;

 reg busy_r = 0;
 reg reset_r = 0;
 reg [7:0]r_cnt = 0;
 assign busy = reset | display | reset_r | busy_r;

 reg [7:0]led_index = 0;
 reg [4:0]bit_index = 0;
 reg [23:0]led_val = 0;
 reg [23:0]leds[0:NB_LEDS-1];

 // Write data
 always @(posedge clk)
 begin
     r_cnt <= 0;
     if(reset) begin
         reset_r <= 1;
     end else if(reset_r) begin
         r_cnt <= r_cnt + 1;
         leds[r_cnt] <= 0;
         if(r_cnt == NB_LEDS - 1) reset_r <= 0;
     end else if(write) leds[addr] <= value;
 end

 // Display data

 reg [15:0]t_cnt = 0;

 localparam IDLE                 = 0;
 localparam TSYM                 = 1;
 localparam RESET                = 2;

 reg [1:0]state = IDLE;

 always @(posedge clk)
 begin

     t_cnt <= t_cnt + 1;
     led_val <= leds[led_index];

     case(state)
         IDLE: begin
             t_cnt <= 0;
             led_index <= 0;
             if(display) begin
                 state <= TSYM;
                 busy_r <= 1;
             end
         end

         TSYM: begin
             if(led_val[bit_index]) begin
                 if(t_cnt == 0)
                     r_led_out <= 1;
                 else if(t_cnt == T1H_C - 1)
                     r_led_out <= 0;
                 else if(t_cnt == T1H_C + T1L_C - 1) begin
                     t_cnt <= 0;
                     bit_index <= bit_index + 1;
                     if(bit_index == 23) begin
                         bit_index <= 0;
                         led_index <= led_index + 1;
                         if(led_index == NB_LEDS - 1) begin
                             state <= RESET;
                         end
                     end
                 end
             end else begin
                 if(t_cnt == 0)
                     r_led_out <= 1;
                 else if(t_cnt == T0H_C - 1)
                     r_led_out <= 0;
                 else if(t_cnt == T0H_C + T0L_C - 1) begin
                     t_cnt <= 0;
                     bit_index <= bit_index + 1;
                     if(bit_index == 23) begin
                         bit_index <= 0;
                         led_index <= led_index + 1;
                         if(led_index == NB_LEDS - 1) begin
                             state <= RESET;
                         end
                     end
                 end
             end
         end

         RESET: begin
             if(t_cnt == RST_C) begin
                 state <= IDLE;
                 busy_r <= 0;
             end
         end
     endcase
 end
endmodule

module main_vc85087 (
 input clk,
 input busy,
 output write,
 output reset,
 output display,
 output [31:0] addr,
 output [23:0] value
);
 reg [7:0]cnt = 0;
 assign addr = cnt;

 reg [23:0]color = 0;
 assign value = color;

 reg r_disp = 0;
 assign display = r_disp;

 reg r_w = 0;
 assign write = r_w;

 always @(posedge clk)
 begin
     r_disp <= 0;
     r_w <= 0;
     if(!busy) begin
         color <= color + 1;
         cnt <= cnt + 1;
         r_w <= 1;
         if(cnt == 149) begin
             r_disp <= 1;
             cnt <= 0;
         end
     end
 end
endmodule