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Matisse THM Block

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Jan 20th, 2021
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  1. - BLOCK_NAME: 'THM'
  2. - DESCRIPTION: 'Thermal (THM)'
  3.  
  4. Registers:
  5. CG_MULT_THERMAL_CTRL (smn_addr_map:0x59978,iod_smn_addr_map:0x59978) 32bit:
  6. 3:0 TS_FILTER
  7. - 0: None
  8. - 1: F(n) = (T(n) + F(n-1))/2
  9. 8:4 UNUSED
  10. 9 THERMAL_RANGE_RST
  11. 27:20 TEMP_SEL
  12.  
  13. CG_MULT_THERMAL_STATUS (smn_addr_map:0x5997c,iod_smn_addr_map:0x5997c) 32bit (R):
  14. 8:0 ASIC_MAX_TEMP
  15. 17:9 CTF_TEMP
  16.  
  17. CG_THERMAL_RANGE (smn_addr_map:0x59980,iod_smn_addr_map:0x59980) 32bit (R):
  18. 8:0 ASIC_T_MAX
  19. 24:16 ASIC_T_MIN
  20.  
  21. SBRMI_APIC_STATUS0 (smn_addr_map:0x59b54,iod_smn_addr_map:0x59b54) 32bit:
  22. 31:0 APICStat0
  23.  
  24. SBRMI_APIC_STATUS1 (smn_addr_map:0x59b58,iod_smn_addr_map:0x59b58) 32bit:
  25. 31:0 APICStat1
  26.  
  27. SBRMI_APIC_STATUS2 (smn_addr_map:0x59b64,iod_smn_addr_map:0x59b64) 32bit:
  28. 31:0 APICStat2
  29.  
  30. SBRMI_APIC_STATUS3 (smn_addr_map:0x59b68,iod_smn_addr_map:0x59b68) 32bit:
  31. 31:0 APICStat3
  32.  
  33. SBRMI_COMMAND (smn_addr_map:0x59b30,iod_smn_addr_map:0x59b30) 32bit:
  34. 7:0 Command(R)
  35. 15:8 WrDataLen(R)
  36. 23:16 RdDataLen(R)
  37. 24 CommandSent
  38. 25 CommandNotSupported
  39. 26 CommandAborted
  40. 31:28 Status
  41.  
  42. SBRMI_CONTROL (smn_addr_map:0x59b2c,iod_smn_addr_map:0x59b2c) 32bit:
  43. 0 READ_CMD_INT_DIS
  44. 1 DPD
  45. 2 DbrdySts
  46.  
  47. SBRMI_CORE_EN_NUMBER (smn_addr_map:0x59b48,iod_smn_addr_map:0x59b48) 32bit:
  48. 7:0 EnabledCoreNum
  49.  
  50. SBRMI_CORE_EN_STATUS0 (smn_addr_map:0x59b4c,iod_smn_addr_map:0x59b4c) 32bit:
  51. 31:0 CoreEnStat0
  52.  
  53. SBRMI_CORE_EN_STATUS1 (smn_addr_map:0x59b50,iod_smn_addr_map:0x59b50) 32bit:
  54. 31:0 CoreEnStat1
  55.  
  56. SBRMI_CORE_EN_STATUS2 (smn_addr_map:0x59b5c,iod_smn_addr_map:0x59b5c) 32bit:
  57. 31:0 CoreEnStat2
  58.  
  59. SBRMI_CORE_EN_STATUS3 (smn_addr_map:0x59b60,iod_smn_addr_map:0x59b60) 32bit:
  60. 31:0 CoreEnStat3
  61.  
  62. SBRMI_MCE_STATUS0 (smn_addr_map:0x59b6c,iod_smn_addr_map:0x59b6c) 32bit:
  63. 31:0 MceStat0
  64.  
  65. SBRMI_MCE_STATUS1 (smn_addr_map:0x59b70,iod_smn_addr_map:0x59b70) 32bit:
  66. 31:0 MceStat1
  67.  
  68. SBRMI_MCE_STATUS2 (smn_addr_map:0x59b74,iod_smn_addr_map:0x59b74) 32bit:
  69. 31:0 MceStat2
  70.  
  71. SBRMI_MCE_STATUS3 (smn_addr_map:0x59b78,iod_smn_addr_map:0x59b78) 32bit:
  72. 31:0 MceStat3
  73.  
  74. SBRMI_READ_DATA0 (smn_addr_map:0x59b40,iod_smn_addr_map:0x59b40) 32bit:
  75. 7:0 RdByte0
  76. 15:8 RdByte1
  77. 23:16 RdByte2
  78. 31:24 RdByte3
  79.  
  80. SBRMI_READ_DATA1 (smn_addr_map:0x59b44,iod_smn_addr_map:0x59b44) 32bit:
  81. 7:0 RdByte4
  82. 15:8 RdByte5
  83. 23:16 RdByte6
  84. 31:24 RdByte7
  85.  
  86. SBRMI_WRITE_DATA0 (smn_addr_map:0x59b34,iod_smn_addr_map:0x59b34) 32bit (R):
  87. 7:0 WrByte0
  88. 15:8 WrByte1
  89. 23:16 WrByte2
  90. 31:24 WrByte3
  91.  
  92. SBRMI_WRITE_DATA1 (smn_addr_map:0x59b38,iod_smn_addr_map:0x59b38) 32bit (R):
  93. 7:0 WrByte4
  94. 15:8 WrByte5
  95. 23:16 WrByte6
  96. 31:24 WrByte7
  97.  
  98. SBRMI_WRITE_DATA2 (smn_addr_map:0x59b3c,iod_smn_addr_map:0x59b3c) 32bit (R):
  99. 7:0 WrByte8
  100. 15:8 WrByte9
  101. 23:16 WrByte10
  102. 31:24 WrByte11
  103.  
  104. SBTSI_REMOTE_TEMP (smn_addr_map:0x59b28,iod_smn_addr_map:0x59b28) 32bit:
  105. 10:0 RemoteTcenSensor
  106. 18:11 RemoteTcenSensorId
  107. 19 RemoteTcenSensorValid
  108.  
  109. SMBUS_BLKRD_CMD_CTRL0 (smn_addr_map:0x59b8c,iod_smn_addr_map:0x59b8c) 32bit:
  110. 7:0 SMB_BLK_RD_CMD0
  111. 15:8 SMB_BLK_RD_CMD1
  112. 23:16 SMB_BLK_RD_CMD2
  113. 31:24 SMB_BLK_RD_CMD3
  114.  
  115. SMBUS_BLKRD_CMD_CTRL1 (smn_addr_map:0x59b90,iod_smn_addr_map:0x59b90) 32bit:
  116. 7:0 SMB_BLK_RD_CMD4
  117. 15:8 SMB_BLK_RD_CMD5
  118. 23:16 SMB_BLK_RD_CMD6
  119. 31:24 SMB_BLK_RD_CMD7
  120.  
  121. SMBUS_BLKWR_CMD_CTRL0 (smn_addr_map:0x59b84,iod_smn_addr_map:0x59b84) 32bit:
  122. 7:0 SMB_BLK_WR_CMD0
  123. 15:8 SMB_BLK_WR_CMD1
  124. 23:16 SMB_BLK_WR_CMD2
  125. 31:24 SMB_BLK_WR_CMD3
  126.  
  127. SMBUS_BLKWR_CMD_CTRL1 (smn_addr_map:0x59b88,iod_smn_addr_map:0x59b88) 32bit:
  128. 7:0 SMB_BLK_WR_CMD4
  129. 15:8 SMB_BLK_WR_CMD5
  130. 23:16 SMB_BLK_WR_CMD6
  131. 31:24 SMB_BLK_WR_CMD7
  132.  
  133. SMBUS_CNTL0 (smn_addr_map:0x59b7c,iod_smn_addr_map:0x59b7c) 32bit:
  134. 0 SMB_DEFAULT_SLV_ADDR_OVERRIDE
  135. 7:1 SMB_DEFAULT_SLV_ADDR
  136. 15:8 SMB_CPL_DUMMY_BYTE
  137. 18:16 SMB_NOTIFY_ARP_MAX_TIMES
  138. 20 THM_READY(R)
  139.  
  140. SMBUS_CNTL1 (smn_addr_map:0x59b80,iod_smn_addr_map:0x59b80) 32bit:
  141. 0 SMB_TIMEOUT_EN
  142. 8:1 SMB_BLK_WR_CMD_EN
  143. 16:9 SMB_BLK_RD_CMD_EN
  144.  
  145. SMBUS_TIMING_CNTL0 (smn_addr_map:0x59b94,iod_smn_addr_map:0x59b94) 32bit:
  146. 21:0 SMB_TIMEOUT_MARGIN
  147. 29:22 SMB_FILTER_LEVEL_CONVERT_MARGIN
  148.  
  149. SMBUS_TIMING_CNTL1 (smn_addr_map:0x59b98,iod_smn_addr_map:0x59b98) 32bit:
  150. 4:0 SMB_DAT_SETUP_TIME_MARGIN
  151. 10:5 SMB_DAT_HOLD_TIME_MARGIN
  152. 19:11 SMB_START_AND_STOP_TIMING_MARGIN
  153. 29:20 SMB_BUS_FREE_MARGIN
  154.  
  155. SMBUS_TIMING_CNTL2 (smn_addr_map:0x59b9c,iod_smn_addr_map:0x59b9c) 32bit:
  156. 12:0 SMB_SMBCLK_HIGHMAX_MARGIN
  157. 26:13 SMBCLK_LEVEL_CTRL_MARGIN
  158.  
  159. SMBUS_TRIGGER_CNTL (smn_addr_map:0x59ba0,iod_smn_addr_map:0x59ba0) 32bit:
  160. 0 SMB_SOFT_RESET_TRIGGER
  161. 8 SMB_NOTIFY_ARP_TRIGGER
  162.  
  163. SMBUS_UDID_CNTL0 (smn_addr_map:0x59ba4,iod_smn_addr_map:0x59ba4) 32bit:
  164. 30:0 SMB_PRBS_INI_SEED
  165. 31 SMB_SRST_REGEN_UDID_EN
  166.  
  167. SMBUS_UDID_CNTL1 (smn_addr_map:0x59ba8,iod_smn_addr_map:0x59ba8) 32bit:
  168. 31:0 SMB_UDID_31_0
  169.  
  170. SMBUS_UDID_CNTL2 (smn_addr_map:0x59bac,iod_smn_addr_map:0x59bac) 32bit:
  171. 0 PEC_SUPPORTED
  172. 3:1 UDID_VERSION
  173. 7:4 SMBUS_VERSION
  174. 8 OEM
  175. 9 ASF
  176. 10 IPMI
  177.  
  178. SMUSBI_ALERT (smn_addr_map:0x59bb4,iod_smn_addr_map:0x59bb4) 32bit:
  179. 0 TXIMPSEL
  180. 1 PD
  181. 2 PU
  182. 3 SCHMEN
  183. 4 S0
  184. 5 S1
  185. 6 RXEN
  186. 7 RXSEL0
  187. 8 RXSEL1
  188. 16 OE_OVERRIDE
  189. 17 OE
  190. 18 A_OVERRIDE
  191. 19 A
  192. 31 Y(R)
  193.  
  194. SMUSBI_CKNBIRESET (smn_addr_map:0x59b1c,iod_smn_addr_map:0x59b1c) 32bit:
  195. 0 CKNBIRESET
  196.  
  197. SMUSBI_ERRATA_STAT_REG (smn_addr_map:0x59b14,iod_smn_addr_map:0x59b14) 32bit (R):
  198. 31:0 ERRATA_STAT_REG
  199.  
  200. SMUSBI_HS_TIMING (smn_addr_map:0x59b24,iod_smn_addr_map:0x59b24) 32bit:
  201. 5:0 HS_SETUP_TIME
  202. 8 HS_SETUP_TIME_OVERRIDE
  203. 23:16 HS_HOLD_TIME
  204. 24 HS_HOLD_TIME_OVERRIDE
  205.  
  206. SMUSBI_IOD0_CCD_SIC (smn_addr_map:0x59bb8,iod_smn_addr_map:0x59bb8) 32bit:
  207. 0 TXIMPSEL
  208. 1 PD
  209. 2 PU
  210. 3 SCHMEN
  211. 4 S0
  212. 5 S1
  213. 6 RXEN
  214. 7 RXSEL0
  215. 8 RXSEL1
  216. 16 OE_OVERRIDE
  217. 17 OE
  218. 18 A_OVERRIDE
  219. 19 A
  220. 31 Y(R)
  221.  
  222. SMUSBI_IOD0_CCD_SID (smn_addr_map:0x59bbc,iod_smn_addr_map:0x59bbc) 32bit:
  223. 0 TXIMPSEL
  224. 1 PD
  225. 2 PU
  226. 3 SCHMEN
  227. 4 S0
  228. 5 S1
  229. 6 RXEN
  230. 7 RXSEL0
  231. 8 RXSEL1
  232. 16 OE_OVERRIDE
  233. 17 OE
  234. 18 A_OVERRIDE
  235. 19 A
  236. 31 Y(R)
  237.  
  238. SMUSBI_IOD0_CCD_SIDIN (smn_addr_map:0x59bc0,iod_smn_addr_map:0x59bc0) 32bit:
  239. 0 TXIMPSEL
  240. 1 PD
  241. 2 PU
  242. 3 SCHMEN
  243. 4 S0
  244. 5 S1
  245. 6 RXEN
  246. 7 RXSEL0
  247. 8 RXSEL1
  248. 16 OE_OVERRIDE
  249. 17 OE
  250. 18 A_OVERRIDE
  251. 19 A
  252. 31 Y(R)
  253.  
  254. SMUSBI_IOD1_CCD_SIC (smn_addr_map:0x59bc4,iod_smn_addr_map:0x59bc4) 32bit:
  255. 0 TXIMPSEL
  256. 1 PD
  257. 2 PU
  258. 3 SCHMEN
  259. 4 S0
  260. 5 S1
  261. 6 RXEN
  262. 7 RXSEL0
  263. 8 RXSEL1
  264. 16 OE_OVERRIDE
  265. 17 OE
  266. 18 A_OVERRIDE
  267. 19 A
  268. 31 Y(R)
  269.  
  270. SMUSBI_IOD1_CCD_SID (smn_addr_map:0x59bc8,iod_smn_addr_map:0x59bc8) 32bit:
  271. 0 TXIMPSEL
  272. 1 PD
  273. 2 PU
  274. 3 SCHMEN
  275. 4 S0
  276. 5 S1
  277. 6 RXEN
  278. 7 RXSEL0
  279. 8 RXSEL1
  280. 16 OE_OVERRIDE
  281. 17 OE
  282. 18 A_OVERRIDE
  283. 19 A
  284. 31 Y(R)
  285.  
  286. SMUSBI_IOD1_CCD_SIDIN (smn_addr_map:0x59bcc,iod_smn_addr_map:0x59bcc) 32bit:
  287. 0 TXIMPSEL
  288. 1 PD
  289. 2 PU
  290. 3 SCHMEN
  291. 4 S0
  292. 5 S1
  293. 6 RXEN
  294. 7 RXSEL0
  295. 8 RXSEL1
  296. 16 OE_OVERRIDE
  297. 17 OE
  298. 18 A_OVERRIDE
  299. 19 A
  300. 31 Y(R)
  301.  
  302. SMUSBI_MP0_CTRL (smn_addr_map:0x59b10,iod_smn_addr_map:0x59b10) 32bit:
  303. 0 MP0_ALERT
  304. 1 APML_EN
  305. 2 TSI_EN
  306. 3 SBAXI_THM_REG_ONLY
  307.  
  308. SMUSBI_MP0_SBIREGADDR (smn_addr_map:0x59b08,iod_smn_addr_map:0x59b08) 32bit:
  309. 7:0 SBI_MP0_REGADDR
  310.  
  311. SMUSBI_MP0_SBIREGDATA (smn_addr_map:0x59b0c,iod_smn_addr_map:0x59b0c) 32bit:
  312. 31:0 SBI_MP0_REGDATA
  313.  
  314. SMUSBI_SBICTRL (smn_addr_map:0x59b18,iod_smn_addr_map:0x59b18) 32bit:
  315. 0 CK_SPRSBIWRDONE(R)
  316. 1 NB_SBISELECT
  317. 4:2 NB_SBIADDR
  318. 5 NB_SBIADDR_OVERRIDE
  319.  
  320. SMUSBI_SBIREGADDR (smn_addr_map:0x59b00,iod_smn_addr_map:0x59b00) 32bit:
  321. 10:0 SBI_REGADDR
  322.  
  323. SMUSBI_SBIREGDATA (smn_addr_map:0x59b04,iod_smn_addr_map:0x59b04) 32bit:
  324. 31:0 SBI_REGDATA
  325.  
  326. SMUSBI_SMBUS (smn_addr_map:0x59bb0,iod_smn_addr_map:0x59bb0) 32bit:
  327. 0 Spare0
  328. 1 Spare1
  329. 2 ResBiasEn
  330. 3 CompSel
  331. 7:4 NG
  332. 9:8 I2cRxSel
  333. 10 PdEn0
  334. 11 PdEn1
  335. 13:12 FallSlewSel
  336. 14 Slewn
  337. 15 SpikeRcEn
  338. 16 SpikeRcSel
  339. 17 CSel0p9
  340. 18 CSel1p1
  341. 19 RSel0p9
  342. 20 RSel1p1
  343. 21 BiasCrtEn
  344. 22 DI2C0
  345. 23 DI2C1
  346. 24 DI2C0_OVERRIDE
  347. 25 DI2C1_OVERRIDE
  348. 30 Y0(R)
  349. 31 Y1(R)
  350.  
  351. SMUSBI_TIMING (smn_addr_map:0x59b20,iod_smn_addr_map:0x59b20) 32bit:
  352. 5:0 SETUP_TIME
  353. 8 SETUP_TIME_OVERRIDE
  354. 23:16 HOLD_TIME
  355. 24 HOLD_TIME_OVERRIDE
  356. 27 DGLT_LMT_OVERRIDE
  357. 31:28 DGLT_LMT
  358.  
  359. THM_CTF_DELAY (smn_addr_map:0x5980c,iod_smn_addr_map:0x5980c) 32bit:
  360. 19:0 CTF_DELAY_CNT
  361.  
  362. THM_DIE1_TEMP (smn_addr_map:0x59954,iod_smn_addr_map:0x59954) 32bit:
  363. 10:0 TEMP
  364. 11 VALID
  365.  
  366. THM_DIE2_TEMP (smn_addr_map:0x59958,iod_smn_addr_map:0x59958) 32bit:
  367. 10:0 TEMP
  368. 11 VALID
  369.  
  370. THM_DIE3_TEMP (smn_addr_map:0x5995c,iod_smn_addr_map:0x5995c) 32bit:
  371. 10:0 TEMP
  372. 11 VALID
  373.  
  374. THM_DIE4_TEMP (smn_addr_map:0x59960,iod_smn_addr_map:0x59960) 32bit:
  375. 10:0 TEMP
  376. 11 VALID
  377.  
  378. THM_DIE5_TEMP (smn_addr_map:0x59964,iod_smn_addr_map:0x59964) 32bit:
  379. 10:0 TEMP
  380. 11 VALID
  381.  
  382. THM_DIE6_TEMP (smn_addr_map:0x59968,iod_smn_addr_map:0x59968) 32bit:
  383. 10:0 TEMP
  384. 11 VALID
  385.  
  386. THM_DIE7_TEMP (smn_addr_map:0x5996c,iod_smn_addr_map:0x5996c) 32bit:
  387. 10:0 TEMP
  388. 11 VALID
  389.  
  390. THM_DIE8_TEMP (smn_addr_map:0x59970,iod_smn_addr_map:0x59970) 32bit:
  391. 10:0 TEMP
  392. 11 VALID
  393.  
  394. THM_DT0_0_COEFF (smn_addr_map:0x59a2c,iod_smn_addr_map:0x59a2c) 32bit:
  395. 6:0 Dt0_1
  396. 13:7 Dt0_2
  397. 20:14 Dt0_3
  398. 27:21 Dt0_4
  399.  
  400. THM_DT0_1_COEFF (smn_addr_map:0x59a30,iod_smn_addr_map:0x59a30) 32bit:
  401. 6:0 Dt0_5
  402. 13:7 Dt0_6
  403. 20:14 Dt0_7
  404. 27:21 Dt0_8
  405.  
  406. THM_DT0_2_COEFF (smn_addr_map:0x59a34,iod_smn_addr_map:0x59a34) 32bit:
  407. 6:0 Dt0_9
  408. 13:7 Dt0_10
  409. 20:14 Dt0_11
  410. 27:21 Dt0_12
  411.  
  412. THM_DT0_3_COEFF (smn_addr_map:0x59a38,iod_smn_addr_map:0x59a38) 32bit:
  413. 6:0 Dt0_13
  414. 13:7 Dt0_14
  415. 20:14 Dt0_15
  416. 27:21 Dt0_16
  417.  
  418. THM_DT0_4_COEFF (smn_addr_map:0x59a3c,iod_smn_addr_map:0x59a3c) 32bit:
  419. 6:0 Dt0_17
  420. 13:7 Dt0_18
  421. 20:14 Dt0_19
  422. 27:21 Dt0_20
  423.  
  424. THM_DT0_5_COEFF (smn_addr_map:0x59a40,iod_smn_addr_map:0x59a40) 32bit:
  425. 6:0 Dt0_21
  426. 13:7 Dt0_22
  427. 20:14 Dt0_23
  428. 27:21 Dt0_24
  429.  
  430. THM_DT0_6_COEFF (smn_addr_map:0x59a44,iod_smn_addr_map:0x59a44) 32bit:
  431. 6:0 Dt0_25
  432. 13:7 Dt0_26
  433. 20:14 Dt0_27
  434. 27:21 Dt0_28
  435.  
  436. THM_DT0_7_COEFF (smn_addr_map:0x59a48,iod_smn_addr_map:0x59a48) 32bit:
  437. 6:0 Dt0_29
  438. 13:7 Dt0_30
  439. 20:14 Dt0_31
  440.  
  441. THM_DT1_0_COEFF (smn_addr_map:0x59a4c,iod_smn_addr_map:0x59a4c) 32bit:
  442. 6:0 Dt1_1
  443. 13:7 Dt1_2
  444. 20:14 Dt1_3
  445. 27:21 Dt1_4
  446.  
  447. THM_DT1_1_COEFF (smn_addr_map:0x59a50,iod_smn_addr_map:0x59a50) 32bit:
  448. 6:0 Dt1_5
  449. 13:7 Dt1_6
  450. 20:14 Dt1_7
  451. 27:21 Dt1_8
  452.  
  453. THM_DT1_2_COEFF (smn_addr_map:0x59a54,iod_smn_addr_map:0x59a54) 32bit:
  454. 6:0 Dt1_9
  455. 13:7 Dt1_10
  456. 20:14 Dt1_11
  457. 27:21 Dt1_12
  458.  
  459. THM_DT1_3_COEFF (smn_addr_map:0x59a58,iod_smn_addr_map:0x59a58) 32bit:
  460. 6:0 Dt1_13
  461. 13:7 Dt1_14
  462. 20:14 Dt1_15
  463. 27:21 Dt1_16
  464.  
  465. THM_DT1_4_COEFF (smn_addr_map:0x59a5c,iod_smn_addr_map:0x59a5c) 32bit:
  466. 6:0 Dt1_17
  467. 13:7 Dt1_18
  468. 20:14 Dt1_19
  469. 27:21 Dt1_20
  470.  
  471. THM_DT1_5_COEFF (smn_addr_map:0x59a60,iod_smn_addr_map:0x59a60) 32bit:
  472. 6:0 Dt1_21
  473. 13:7 Dt1_22
  474. 20:14 Dt1_23
  475. 27:21 Dt1_24
  476.  
  477. THM_DT1_6_COEFF (smn_addr_map:0x59a64,iod_smn_addr_map:0x59a64) 32bit:
  478. 6:0 Dt1_25
  479. 13:7 Dt1_26
  480. 20:14 Dt1_27
  481. 27:21 Dt1_28
  482.  
  483. THM_DT1_7_COEFF (smn_addr_map:0x59a68,iod_smn_addr_map:0x59a68) 32bit:
  484. 6:0 Dt1_29
  485. 13:7 Dt1_30
  486. 20:14 Dt1_31
  487.  
  488. THM_GPIO_IOD0_CCD_THERMTRIP_L_CTRL (smn_addr_map:0x59a24,iod_smn_addr_map:0x59a24) 32bit:
  489. 0 TXIMPSEL
  490. 1 PD
  491. 2 PU
  492. 3 SCHMEN
  493. 4 S0
  494. 5 S1
  495. 6 RXEN
  496. 7 RXSEL0
  497. 8 RXSEL1
  498. 16 OE_OVERRIDE
  499. 17 OE
  500. 18 A_OVERRIDE
  501. 19 A
  502. 31 Y(R)
  503.  
  504. THM_GPIO_IOD1_CCD_THERMTRIP_L_CTRL (smn_addr_map:0x59a28,iod_smn_addr_map:0x59a28) 32bit:
  505. 0 TXIMPSEL
  506. 1 PD
  507. 2 PU
  508. 3 SCHMEN
  509. 4 S0
  510. 5 S1
  511. 6 RXEN
  512. 7 RXSEL0
  513. 8 RXSEL1
  514. 16 OE_OVERRIDE
  515. 17 OE
  516. 18 A_OVERRIDE
  517. 19 A
  518. 31 Y(R)
  519.  
  520. THM_GPIO_PROCHOT_CTRL (smn_addr_map:0x59810,iod_smn_addr_map:0x59810) 32bit:
  521. 0 TXIMPSEL
  522. 1 PD
  523. 2 PU
  524. 3 SCHMEN
  525. 4 S0
  526. 5 S1
  527. 6 RXEN
  528. 7 RXSEL0
  529. 8 RXSEL1
  530. 16 OE_OVERRIDE
  531. 17 OE
  532. 18 A_OVERRIDE
  533. 19 A
  534. 31 Y(R)
  535.  
  536. THM_PWRMGT (smn_addr_map:0x59a1c,iod_smn_addr_map:0x59a1c) 32bit:
  537. 0 CLK_GATE_EN
  538. 1 CLK_GATE_ST(R)
  539. 2 DBG_CLK_GATE_EN
  540. 23:8 CLK_GATE_MAX_CNT
  541.  
  542. THM_SW_TEMP (smn_addr_map:0x59974,iod_smn_addr_map:0x59974) 32bit:
  543. 8:0 SW_TEMP
  544.  
  545. THM_TCON_CUR_TMP (smn_addr_map:0x59800,iod_smn_addr_map:0x59800) 32bit:
  546. 4:0 PER_STEP_TIME_UP
  547. 6:5 TMP_MAX_DIFF_UP
  548. 7 TMP_SLEW_DN_EN
  549. 12:8 PER_STEP_TIME_DN
  550. 17:16 CUR_TEMP_TJ_SEL
  551. 18 CUR_TEMP_TJ_SLEW_SEL
  552. 19 CUR_TEMP_RANGE_SEL
  553. 20 MCM_EN
  554. 31:21 CUR_TEMP
  555.  
  556. THM_TCON_HTC (smn_addr_map:0x59804,iod_smn_addr_map:0x59804) 32bit:
  557. 0 HTC_EN
  558. 2 EXTERNAL_PROCHOT(R)
  559. 3 INTERNAL_PROCHOT(R)
  560. 4 HTC_ACTIVE(R)
  561. 5 HTC_ACTIVE_LOG
  562. 8 HTC_DIAG
  563. 9 DIS_PROCHOT_PIN_OUT
  564. 10 HTC_TO_IH_EN
  565. 11 PROCHOT_TO_IH_EN
  566. 14:12 PROCHOT_EVENT_SRC
  567. 15 DIS_PROCHOT_PIN_IN
  568. 22:16 HTC_TMP_LMT
  569. 26:23 HTC_HYST_LMT
  570. 28:27 HTC_SLEW_SEL
  571.  
  572. THM_TCON_LOCAL0 (smn_addr_map:0x599cc,iod_smn_addr_map:0x599cc) 32bit:
  573. 1 TMON0_PwrDn_Dis
  574. 2 TMON1_PwrDn_Dis
  575.  
  576. THM_TCON_LOCAL1 (smn_addr_map:0x599d0,iod_smn_addr_map:0x599d0) 32bit:
  577. 0 Turn_Off_TMON0
  578. 1 Turn_Off_TMON1
  579. 4 PowerDownTmon0(R)
  580. 5 PowerDownTmon1(R)
  581.  
  582. THM_TCON_LOCAL10 (smn_addr_map:0x599f4,iod_smn_addr_map:0x599f4) 32bit (R):
  583. 7:0 TMON0_Tj_Max_RS_ID
  584.  
  585. THM_TCON_LOCAL11 (smn_addr_map:0x599f8,iod_smn_addr_map:0x599f8) 32bit (R):
  586. 10:0 Tj_Max_TMON1
  587.  
  588. THM_TCON_LOCAL12 (smn_addr_map:0x599fc,iod_smn_addr_map:0x599fc) 32bit (R):
  589. 7:0 TMON1_Tj_Max_RS_ID
  590.  
  591. THM_TCON_LOCAL13 (smn_addr_map:0x59a00,iod_smn_addr_map:0x59a00) 32bit (R):
  592. 0 boot_done
  593.  
  594. THM_TCON_LOCAL2 (smn_addr_map:0x599d4,iod_smn_addr_map:0x599d4) 32bit:
  595. 1:0 TMON_init_delay
  596. 3:2 TMON_pwrup_stagger_time
  597. 5 short_stagger_count
  598. 6 sbtsi_use_corrected
  599. 10 temp_read_skip_scale
  600. 11 skip_scale_correction
  601.  
  602. THM_TCON_LOCAL3 (smn_addr_map:0x599d8,iod_smn_addr_map:0x599d8) 32bit (R):
  603. 10:0 Global_TMAX
  604.  
  605. THM_TCON_LOCAL4 (smn_addr_map:0x599dc,iod_smn_addr_map:0x599dc) 32bit (R):
  606. 7:0 Global_TMAX_ID
  607.  
  608. THM_TCON_LOCAL5 (smn_addr_map:0x599e0,iod_smn_addr_map:0x599e0) 32bit (R):
  609. 10:0 Global_TMIN
  610.  
  611. THM_TCON_LOCAL6 (smn_addr_map:0x599e4,iod_smn_addr_map:0x599e4) 32bit (R):
  612. 7:0 Global_TMIN_ID
  613.  
  614. THM_TCON_LOCAL7 (smn_addr_map:0x599e8,iod_smn_addr_map:0x599e8) 32bit (R):
  615. 7:0 THERMID
  616.  
  617. THM_TCON_LOCAL8 (smn_addr_map:0x599ec,iod_smn_addr_map:0x599ec) 32bit (R):
  618. 10:0 THERMMAX
  619.  
  620. THM_TCON_LOCAL9 (smn_addr_map:0x599f0,iod_smn_addr_map:0x599f0) 32bit (R):
  621. 10:0 Tj_Max_TMON0
  622.  
  623. THM_TCON_THERM_TRIP (smn_addr_map:0x59808,iod_smn_addr_map:0x59808) 32bit:
  624. 0 CTF_PAD_POLARITY
  625. 1 THERM_TP(R)
  626. 2 CTF_THRESHOLD_EXCEEDED(R)
  627. 3 THERM_TP_SENSE(R)
  628. 4 RSVD2
  629. 5 THERM_TP_EN
  630. 13:6 THERM_TP_LMT
  631. 30:14 RSVD3
  632. 31 SW_THERM_TP
  633.  
  634. THM_THERMAL_INT_CTRL (smn_addr_map:0x5982c,iod_smn_addr_map:0x5982c) 32bit:
  635. 7:0 DIG_THERM_INTH
  636. 15:8 DIG_THERM_INTL
  637. 23:16 TEMP_THRESHOLD
  638. 24 THERM_INTH_MASK
  639. - 0: Mask Disabled
  640. - 1: Mask Enabled
  641. 25 THERM_INTL_MASK
  642. - 0: Mask Disabled
  643. - 1: Mask Enabled
  644. 26 THERM_TRIGGER_MASK
  645. - 0: Mask Disabled
  646. - 1: Mask Enabled
  647. 27 THERM_PROCHOT_MASK
  648. - 0: Mask Disabled
  649. - 1: Mask Enabled
  650. 28 THERM_IH_HW_ENA
  651. - 0: Firmware controls thermal trigger
  652. - 1: TCON_GN_tm_Gtemp controls thermal trigger
  653. 31:29 MAX_IH_CREDIT
  654.  
  655. THM_THERMAL_INT_ENA (smn_addr_map:0x59828,iod_smn_addr_map:0x59828) 32bit (W):
  656. 0 THERM_INTH_SET
  657. - 1: Set thermal L2H interrupt
  658. 1 THERM_INTL_SET
  659. - 1: Set thermal H2L interrupt
  660. 2 THERM_TRIGGER_SET
  661. - 1: Set thermal trigger(ThermTrigger) interrupt
  662. 3 THERM_INTH_CLR
  663. - 1: Clear thermal L2H interrupt
  664. 4 THERM_INTL_CLR
  665. - 1: Clear thermal H2L interrupt
  666. 5 THERM_TRIGGER_CLR
  667. - 1: Clear thermal trigger(ThermTrigger) interrupt
  668.  
  669. THM_THERMAL_INT_STATUS (smn_addr_map:0x59830,iod_smn_addr_map:0x59830) 32bit (R):
  670. 0 THERM_INTH_DETECT
  671. - 1: Thermal L2H interrupt detected
  672. 1 THERM_INTL_DETECT
  673. - 1: Thermal H2L interrupt detected
  674. 2 THERM_TRIGGER_DETECT
  675. - 1: Thermal trigger interrupt detected
  676. 3 THERM_PROCHOT_DETECT
  677. - 1: CNB thermal trigger interrupt detected
  678.  
  679. THM_TMON0_COEFF (smn_addr_map:0x5998c,iod_smn_addr_map:0x5998c) 32bit:
  680. 10:0 C_OFFSET
  681. 17:11 D
  682.  
  683. THM_TMON0_CTRL (smn_addr_map:0x598b8,iod_smn_addr_map:0x598b8) 32bit:
  684. 0 POWER_DOWN
  685. 8:1 BGADJ
  686. 9 BGADJ_MODE
  687. 10 TMON_PAUSE
  688. 11 INT_MEAS_EN
  689. 12 DEBUG_MODE
  690. 13 EN_CFG_SERDES
  691.  
  692. THM_TMON0_CTRL2 (smn_addr_map:0x598bc,iod_smn_addr_map:0x598bc) 32bit:
  693. 15:0 RDIL_PRESENT
  694. 31:16 RDIR_PRESENT
  695.  
  696. THM_TMON0_DEBUG (smn_addr_map:0x598c0,iod_smn_addr_map:0x598c0) 32bit:
  697. 4:0 DEBUG_RDI
  698. 15:5 DEBUG_Z
  699.  
  700. THM_TMON0_INT_DATA (smn_addr_map:0x598b4,iod_smn_addr_map:0x598b4) 32bit (R):
  701. 10:0 Z
  702. 11 VALID
  703. 23:12 TEMP
  704.  
  705. THM_TMON0_RDIL0_DATA (smn_addr_map:0x59834,iod_smn_addr_map:0x59834) 32bit (R):
  706. 10:0 Z
  707. 11 VALID
  708. 23:12 TEMP
  709.  
  710. THM_TMON0_RDIL10_DATA (smn_addr_map:0x5985c,iod_smn_addr_map:0x5985c) 32bit (R):
  711. 10:0 Z
  712. 11 VALID
  713. 23:12 TEMP
  714.  
  715. THM_TMON0_RDIL11_DATA (smn_addr_map:0x59860,iod_smn_addr_map:0x59860) 32bit (R):
  716. 10:0 Z
  717. 11 VALID
  718. 23:12 TEMP
  719.  
  720. THM_TMON0_RDIL12_DATA (smn_addr_map:0x59864,iod_smn_addr_map:0x59864) 32bit (R):
  721. 10:0 Z
  722. 11 VALID
  723. 23:12 TEMP
  724.  
  725. THM_TMON0_RDIL13_DATA (smn_addr_map:0x59868,iod_smn_addr_map:0x59868) 32bit (R):
  726. 10:0 Z
  727. 11 VALID
  728. 23:12 TEMP
  729.  
  730. THM_TMON0_RDIL14_DATA (smn_addr_map:0x5986c,iod_smn_addr_map:0x5986c) 32bit (R):
  731. 10:0 Z
  732. 11 VALID
  733. 23:12 TEMP
  734.  
  735. THM_TMON0_RDIL15_DATA (smn_addr_map:0x59870,iod_smn_addr_map:0x59870) 32bit (R):
  736. 10:0 Z
  737. 11 VALID
  738. 23:12 TEMP
  739.  
  740. THM_TMON0_RDIL1_DATA (smn_addr_map:0x59838,iod_smn_addr_map:0x59838) 32bit (R):
  741. 10:0 Z
  742. 11 VALID
  743. 23:12 TEMP
  744.  
  745. THM_TMON0_RDIL2_DATA (smn_addr_map:0x5983c,iod_smn_addr_map:0x5983c) 32bit (R):
  746. 10:0 Z
  747. 11 VALID
  748. 23:12 TEMP
  749.  
  750. THM_TMON0_RDIL3_DATA (smn_addr_map:0x59840,iod_smn_addr_map:0x59840) 32bit (R):
  751. 10:0 Z
  752. 11 VALID
  753. 23:12 TEMP
  754.  
  755. THM_TMON0_RDIL4_DATA (smn_addr_map:0x59844,iod_smn_addr_map:0x59844) 32bit (R):
  756. 10:0 Z
  757. 11 VALID
  758. 23:12 TEMP
  759.  
  760. THM_TMON0_RDIL5_DATA (smn_addr_map:0x59848,iod_smn_addr_map:0x59848) 32bit (R):
  761. 10:0 Z
  762. 11 VALID
  763. 23:12 TEMP
  764.  
  765. THM_TMON0_RDIL6_DATA (smn_addr_map:0x5984c,iod_smn_addr_map:0x5984c) 32bit (R):
  766. 10:0 Z
  767. 11 VALID
  768. 23:12 TEMP
  769.  
  770. THM_TMON0_RDIL7_DATA (smn_addr_map:0x59850,iod_smn_addr_map:0x59850) 32bit (R):
  771. 10:0 Z
  772. 11 VALID
  773. 23:12 TEMP
  774.  
  775. THM_TMON0_RDIL8_DATA (smn_addr_map:0x59854,iod_smn_addr_map:0x59854) 32bit (R):
  776. 10:0 Z
  777. 11 VALID
  778. 23:12 TEMP
  779.  
  780. THM_TMON0_RDIL9_DATA (smn_addr_map:0x59858,iod_smn_addr_map:0x59858) 32bit (R):
  781. 10:0 Z
  782. 11 VALID
  783. 23:12 TEMP
  784.  
  785. THM_TMON0_RDIR0_DATA (smn_addr_map:0x59874,iod_smn_addr_map:0x59874) 32bit (R):
  786. 10:0 Z
  787. 11 VALID
  788. 23:12 TEMP
  789.  
  790. THM_TMON0_RDIR10_DATA (smn_addr_map:0x5989c,iod_smn_addr_map:0x5989c) 32bit (R):
  791. 10:0 Z
  792. 11 VALID
  793. 23:12 TEMP
  794.  
  795. THM_TMON0_RDIR11_DATA (smn_addr_map:0x598a0,iod_smn_addr_map:0x598a0) 32bit (R):
  796. 10:0 Z
  797. 11 VALID
  798. 23:12 TEMP
  799.  
  800. THM_TMON0_RDIR12_DATA (smn_addr_map:0x598a4,iod_smn_addr_map:0x598a4) 32bit (R):
  801. 10:0 Z
  802. 11 VALID
  803. 23:12 TEMP
  804.  
  805. THM_TMON0_RDIR13_DATA (smn_addr_map:0x598a8,iod_smn_addr_map:0x598a8) 32bit (R):
  806. 10:0 Z
  807. 11 VALID
  808. 23:12 TEMP
  809.  
  810. THM_TMON0_RDIR14_DATA (smn_addr_map:0x598ac,iod_smn_addr_map:0x598ac) 32bit (R):
  811. 10:0 Z
  812. 11 VALID
  813. 23:12 TEMP
  814.  
  815. THM_TMON0_RDIR15_DATA (smn_addr_map:0x598b0,iod_smn_addr_map:0x598b0) 32bit (R):
  816. 10:0 Z
  817. 11 VALID
  818. 23:12 TEMP
  819.  
  820. THM_TMON0_RDIR1_DATA (smn_addr_map:0x59878,iod_smn_addr_map:0x59878) 32bit (R):
  821. 10:0 Z
  822. 11 VALID
  823. 23:12 TEMP
  824.  
  825. THM_TMON0_RDIR2_DATA (smn_addr_map:0x5987c,iod_smn_addr_map:0x5987c) 32bit (R):
  826. 10:0 Z
  827. 11 VALID
  828. 23:12 TEMP
  829.  
  830. THM_TMON0_RDIR3_DATA (smn_addr_map:0x59880,iod_smn_addr_map:0x59880) 32bit (R):
  831. 10:0 Z
  832. 11 VALID
  833. 23:12 TEMP
  834.  
  835. THM_TMON0_RDIR4_DATA (smn_addr_map:0x59884,iod_smn_addr_map:0x59884) 32bit (R):
  836. 10:0 Z
  837. 11 VALID
  838. 23:12 TEMP
  839.  
  840. THM_TMON0_RDIR5_DATA (smn_addr_map:0x59888,iod_smn_addr_map:0x59888) 32bit (R):
  841. 10:0 Z
  842. 11 VALID
  843. 23:12 TEMP
  844.  
  845. THM_TMON0_RDIR6_DATA (smn_addr_map:0x5988c,iod_smn_addr_map:0x5988c) 32bit (R):
  846. 10:0 Z
  847. 11 VALID
  848. 23:12 TEMP
  849.  
  850. THM_TMON0_RDIR7_DATA (smn_addr_map:0x59890,iod_smn_addr_map:0x59890) 32bit (R):
  851. 10:0 Z
  852. 11 VALID
  853. 23:12 TEMP
  854.  
  855. THM_TMON0_RDIR8_DATA (smn_addr_map:0x59894,iod_smn_addr_map:0x59894) 32bit (R):
  856. 10:0 Z
  857. 11 VALID
  858. 23:12 TEMP
  859.  
  860. THM_TMON0_RDIR9_DATA (smn_addr_map:0x59898,iod_smn_addr_map:0x59898) 32bit (R):
  861. 10:0 Z
  862. 11 VALID
  863. 23:12 TEMP
  864.  
  865. THM_TMON0_REMOTE_END (smn_addr_map:0x59cfc,iod_smn_addr_map:0x59cfc) 32bit:
  866. 31:0 DATA
  867.  
  868. THM_TMON0_REMOTE_START (smn_addr_map:0x59c00,iod_smn_addr_map:0x59c00) 32bit:
  869. 31:0 DATA
  870.  
  871. THM_TMON1_REMOTE_END (smn_addr_map:0x59dfc,iod_smn_addr_map:0x59dfc) 32bit:
  872. 31:0 DATA
  873.  
  874. THM_TMON1_REMOTE_START (smn_addr_map:0x59d00,iod_smn_addr_map:0x59d00) 32bit:
  875. 31:0 DATA
  876.  
  877. THM_TMON2_REMOTE_END (smn_addr_map:0x59efc,iod_smn_addr_map:0x59efc) 32bit:
  878. 31:0 DATA
  879.  
  880. THM_TMON2_REMOTE_START (smn_addr_map:0x59e00,iod_smn_addr_map:0x59e00) 32bit:
  881. 31:0 DATA
  882.  
  883. THM_TMON3_REMOTE_END (smn_addr_map:0x59ffc,iod_smn_addr_map:0x59ffc) 32bit:
  884. 31:0 DATA
  885.  
  886. THM_TMON3_REMOTE_START (smn_addr_map:0x59f00,iod_smn_addr_map:0x59f00) 32bit:
  887. 31:0 DATA
  888.  
  889. THM_TMON_CONFIG (smn_addr_map:0x59984,iod_smn_addr_map:0x59984) 32bit:
  890. 2:0 NUM_ACQ
  891. 3 FORCE_MAX_ACQ
  892. 4 RDI_INTERLEAVE
  893. 5 CONFIG_SOURCE
  894. 6 RE_CALIB_EN
  895. 31:21 Z
  896.  
  897. THM_TMON_CONFIG2 (smn_addr_map:0x59988,iod_smn_addr_map:0x59988) 32bit:
  898. 11:0 A
  899. 17:12 B
  900. 28:18 C
  901. 29 K
  902.  
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