type order_array is array(0 to 7) of std_logic_vector(11 downto 0);

port(enable : in std_logic;

        clk : in std_logic;

        inarray : in order_array;

        outarray : out order_array);

loop1 : for j in 0 to 6 generate

    loop2 : for i in 0 to 6-j generate

        process(clk, inarray)

            variable temp : std_logic_vector(11 downto 0);

            variable sorted_array : order_array;

            begin

                sorted_array := inarray;

                if(rising_edge(clk)) then

                    if(enable='1') then

                        if(unsigned(sorted_array(i)) < unsigned(sorted_array(i+1))) then

                            temp := sorted_array(i);

                            sorted_array(i) := sorted_array(i + 1);

                            sorted_array(i + 1) := temp;

                        end if;

                    end if;

                    outarray<=sorted_array;

                end if;

            end process;

        end generate;

      end generate;