module labL;
reg [1:0] a, b, c_in, expect;
wire [1:0] z;
integer i, j, k;
yMux2 mux(z, a, b, c_in);

initial
begin
  for(i = 0; i < 2; i = i + 1)
    begin
      for(j = 0; j < 2; j = j + 1)
        begin
          for(k = 0; k < 2; k = k + 1)
            begin
            a = i;
            b = j;
            c_in = k;
            // expect = (a & ~b) | (b & c_in);
            if(expect === z)
              $display("PASS: a = %b, b = %b, c = %b, z = %b", a, b, c_in, z);
            else
              $display("FAIL: a = %b, b = %b, c = %b, z = %b", a, b, c_in, z);
          end
      end
  end
  $finish;
  end
  endmodule