b reset            ; RESET 0x00000000, Reset
    b hang             ; UNDEF 0x00000004, Undefined Instruction
    b hang             ; SWI   0x00000008, Software Interrupt
    b hang             ; PABT  0x0000000C, Prefetch Abort

    b hang             ; DABT  0x00000010, Data Abort
    b hang             ; RSV   0x00000014, Reserved
    ldr pc, [irq_isr]  ; IRQ   0x00000018, Interrupt Request
    b hang             ; FIQ   0x0000001C, Fast Interrupt Request

    b hang
    b hang
    b hang
    b hang

    b hang
    b hang
    b hang
    b hang

    TIMER_CVR    EQU 0x04 ; Current Value Register, TimerXValue
    TIMER_CR     EQU 0x08 ; Control Register, TimerXControl
    TIMER_INTCLR EQU 0x0C ; Interrupt Clear Register, TimerXIntClr
    TIMER_BGLOAD EQU 0x18 ; Background Load Register

    irq_isr: dd irq_isr_addr
;*********************************
;* IRQ Interrupt Service Routine *
;*********************************
    irq_isr_addr:
    ;push {r0-r12, r14}
    ;pop {r0-r12, r14}
    subs pc, r14, #4

reset:
    mov sp, #0x20000
;****************************************
;*         Enable Timer0 and IRQs       *
;****************************************
    mrs r0, cpsr
    bic r0, r0, #0x80 ; Clear IRQ Disable
    msr cpsr_c, r0

    ldr r1, [TIMER_BASE]
    add r1, TIMER_CR
    mov r0, #0
    str r0, [r1]

    ldr r0, [TIMER_COUNT]
    ldr r1, [TIMER_BASE]
    ldr r2, [TIMER_BGLOAD]
    str r0, [r1]
    str r0, [r2]

    ldr r1, [TIMER_BASE]
    add r1, TIMER_INTCLR
    mov r2, #0
    str r2, [r1]

    mov r0, #0xE2 ; Timer Enable, Periodic Mode, IRQ ON, Prescale = 0, 32 bit, Wrapping Mode
    ldr r1, [TIMER_BASE]
    add r1, TIMER_CR
    str r0, [r1]

    mov r0, #0x10
    ldr r1, [VIC_INTENABLE]
    str r0, [r1]

    b  mainloop
    TIMER_BASE: dd 0x101E2000
    TIMER_COUNT: dd 1000000
    VIC_BASE: dd 0x10140000
    VIC_IRQSTATUS: dd (0x10140000 + 0x00)
    VIC_FIGSTATUS: dd (0x10140000 + 0x04)
    VIC_RAWINTR:   dd (0x10140000 + 0x08)
    VIC_INTSELECT: dd (0x10140000 + 0x0C)
    VIC_INTENABLE: dd (0x10140000 + 0x10)
    VIC_INTCLEAR:  dd (0x10140000 + 0x14)
    VIC_SOFTINT:   dd (0x10140000 + 0x18)

hang:
    b hang
;****************************************
;*            Kernel Mainloop           *
;****************************************
mainloop:
;    ldr r1, [pc, 4]
;    bl uart_put32
;    b mainloop
;    dd 0x50505050

     ldr r0, [TIMER_BASE]
     add r0, TIMER_CVR
     ldr r1, [r0]
     bl uart_put32
     b mainloop
;****************************************
;* UART Write 32 Bit Value              *
;* Input: R1 Value to be written        *
;* Output: None                         *
;****************************************
uart_put32:
    ldr r0, [pc, 4]   ; PC + 16
    str r1, [r0]
    bx lr
    dd 0x101f1000